公开(公告)号：US11653490B2

公开(公告)日：2023-05-16

申请号：US17471778

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokho Shin ,  Taegyu Kang ,  Byeungmoo Kang ,  Joongchan Shin

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

公开(公告)号：US20240074155A1

公开(公告)日：2024-02-29

申请号：US18236143

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyuk Kim ,  Taegyu Kang ,  Seokho Shin ,  Kiseok Lee ,  Sangho Lee ,  Keunnam Kim ,  Seokhan Park ,  Joongchan Shin ,  Moonyoung Jeong ,  Eunju Cho

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.

公开(公告)号：US20250098153A1

公开(公告)日：2025-03-20

申请号：US18657892

申请日：2024-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegyu Kang ,  Joongchan Shin ,  Keunui Kim ,  Myeongseon Kim ,  Eunsuk Jang

IPC: H10B12/00

Abstract: A semiconductor device includes: a bit line on a substrate and extending in a first direction; a first word line on the bit line extending in a second direction crossing the first direction; a second word line extending in the second direction on the bit line and spaced from the first word line; first activating patterns on the bit line between the first and second word lines; second activating patterns on the bit line between the first and second word lines; a back gate electrode crossing the bit line and extending in the second direction between the first and second activating patterns; and first and second back gate capping patterns overlapping the back gate electrode. The first back gate capping pattern defines a gap region on the back gate electrode not overlapping the first and second activating patterns, and the second back gate capping pattern is in the gap region.

公开(公告)号：US20140327155A1

公开(公告)日：2014-11-06

申请号：US14134589

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegyu Kang ,  Minchul Kim ,  Sung-Jin Kim ,  Kyeongjun Song

IPC: H01L23/28 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/00012

Abstract: A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip mounted on a surface of the lower substrate, connection terminals between the lower substrate and the lower semiconductor chip, and a protection film covering the lower semiconductor chip. An upper package is spaced apart from the lower package on an upper surface of the lower substrate, the upper package comprising an upper substrate and an upper semiconductor chip. Connections are present between the lower substrate and the upper substrate to horizontally surround the lower semiconductor chip. A molding film is on the upper surface of the lower substrate to fill spaces between the connection terminals and the connections. An uppermost surface of the protection film is positioned at substantially a same vertical level as an uppermost surface of the molding film and is spaced apart from the upper package.

Abstract translation: 半导体封装包括下封装，其包括下基板，安装在下基板的表面上的下半导体芯片，下基板和下半导体芯片之间的连接端子以及覆盖下半导体芯片的保护膜。 上封装在下基板的上表面上与下封装隔开，上封装包括上基板和上半导体芯片。 连接存在于下基板和上基板之间以水平地围绕下半导体芯片。 成型膜位于下基板的上表面上，以填充连接端子和连接件之间的空间。 保护膜的最上表面位于与成型膜的最上表面大致相同的垂直高度，并且与上包装件间隔开。

公开(公告)号：US20150318270A1

公开(公告)日：2015-11-05

申请号：US14796519

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegyu Kang ,  Minchul Kim ,  Sung-Jin Kim ,  Kyeongjun Song

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/00012

Abstract: A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip mounted on a surface of the lower substrate, connection terminals between the lower substrate and the lower semiconductor chip, and a protection film covering the lower semiconductor chip. An upper package is spaced apart from the lower package on an upper surface of the lower substrate, the upper package comprising an upper substrate and an upper semiconductor chip. Connections are present between the lower substrate and the upper substrate to horizontally surround the lower semiconductor chip. A molding film is on the upper surface of the lower substrate to fill spaces between the connection terminals and the connections. An uppermost surface of the protection film is positioned at substantially a same vertical level as an uppermost surface of the molding film and is spaced apart from the upper package.

Abstract translation: 半导体封装包括下封装，其包括下基板，安装在下基板的表面上的下半导体芯片，下基板和下半导体芯片之间的连接端子以及覆盖下半导体芯片的保护膜。 上封装在下基板的上表面上与下封装隔开，上封装包括上基板和上半导体芯片。 连接存在于下基板和上基板之间以水平地围绕下半导体芯片。 成型膜位于下基板的上表面上，以填充连接端子和连接件之间的空间。 保护膜的最上表面位于与成型膜的最上表面大致相同的垂直高度，并且与上包装件间隔开。