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    SEMICONDUCTOR PACKAGES AND RELATED METHODS
    1.
    发明公开
    SEMICONDUCTOR PACKAGES AND RELATED METHODS 审中-公开

    公开(公告)号：US20240355638A1

    公开(公告)日：2024-10-24

    申请号：US18760515

    申请日：2024-07-01

    申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    发明人： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

    IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/498

    CPC分类号： H01L21/4821 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49534 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49861

    摘要： Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

    FAN-OUT PACKAGING METHOD AND PACKAGING STRUCTURE THEREOF
    2.
    发明公开
    FAN-OUT PACKAGING METHOD AND PACKAGING STRUCTURE THEREOF 审中-公开

    公开(公告)号：US20240321825A1

    公开(公告)日：2024-09-26

    申请号：US18680211

    申请日：2024-05-31

    申请人： TONGFU MICROELECTRONICS CO., LTD.

    发明人： Maohua DU

    IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/28

    CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L23/28 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/96

    摘要： A fan-out packaging method and packaging structure are provided. The method includes: providing a wafer carrier, a panel carrier, and groups of first chips; fixing first surfaces of the groups of first chips on the wafer carrier; forming a first plastic encapsulation layer on second surfaces of the groups of first chips; separating the groups of first chips from the wafer carrier; forming a high-density interconnection wiring layer on the first surfaces of the groups of first chips; cutting the groups of first chips; fixing one side of the groups of first chips with the high-density interconnection wiring layer on the panel carrier; forming a second plastic encapsulation layer on another side of the groups of first chips away from the high-density interconnection wiring layer; separating the groups of first chips from the panel carrier; and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.

    SEMICONDUCTOR PACKAGING METHOD AND THE STRUCTURE FORMED THEREFROM
    3.
    发明公开
    SEMICONDUCTOR PACKAGING METHOD AND THE STRUCTURE FORMED THEREFROM 审中-公开

    公开(公告)号：US20240258260A1

    公开(公告)日：2024-08-01

    申请号：US18422034

    申请日：2024-01-25

    申请人： PEP INNOVATION PTE. LTD.

    发明人： Hwee Seng Chew

    IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/28

    CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L24/20 ,  H01L2224/19 ,  H01L2224/21

    摘要： The present application discloses a semiconductor structure including one or more dies, a protective layer formed on a die active surface, pre-vias formed in the protective layer, and a molding layer encapsulating the die(s) and the protective layer. The die has a die back surface exposed from the molding layer, and the molding layer has a molding thickness larger than a die thickness and a thickness of the protective layer combined for forming a cavity contour. The semiconductor structure also includes a conductive layer formed conformally to the cavity contour for forming a concave contour of the conductive layer. The present application also discloses methods of making the semiconductor structure having a sacrificial layer for solving an issue of die cracking during a thinning process such as backgrinding to a reconstituted panel with the dies embedded within the molding layer.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11923261B2

    公开(公告)日：2024-03-05

    申请号：US17487674

    申请日：2021-09-28

    申请人： SANSHA ELECTRIC MANUFACTURING CO., LTD.

    发明人： Koutarou Maeda

    IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/053 ,  H01L23/31

    CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/053

    摘要： A semiconductor chip is provided on a semiconductor circuit base on one surface of an insulating substrate. A reinforcement and balance base is provided on the one surface of the insulating substrate spaced to the semiconductor circuit base. The insulating substrate 4, the semiconductor circuit base, the semiconductor chip, and the reinforcement and balance base are sealed into a resin-molded sealing body. The sealing body has resin non-adhering portions.