公开(公告)号：US12125755B2

公开(公告)日：2024-10-22

申请号：US18359923

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Feng-Cheng Hsu ,  Shuo-Mao Chen

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/13 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/16148 ,  H01L2224/16238

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, and a semiconductor device. The interposer substrate is disposed over the package substrate, wherein the interposer substrate has a bottom surface facing the package substrate and a first cavity formed on the bottom surface. The semiconductor device is disposed in the first cavity. The package substrate has a top surface facing the interposer substrate and a second cavity formed on the top surface, wherein the second cavity is configured to accommodate the semiconductor device.

公开(公告)号：US20240087903A1

公开(公告)日：2024-03-14

申请号：US18510646

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L21/304 ,  B28D5/00 ,  H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L21/3043 ,  B28D5/00 ,  H01L21/02109 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/023 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/19011 ,  H01L2924/19106 ,  H01L2924/3511

Abstract: Provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. The through via is laterally aside the die. The encapsulant laterally encapsulates the through via and the die. The warpage controlling layer covers the encapsulant and the die. The cap is laterally aside the warpage controlling layer and on the through via. The cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.

公开(公告)号：US11915992B2

公开(公告)日：2024-02-27

申请号：US17679372

申请日：2022-02-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Chin-Hua Wang

IPC: H01L23/367 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L21/4871 ,  H01L21/56 ,  H01L25/18 ,  H01L25/50

Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

公开(公告)号：US11810830B2

公开(公告)日：2023-11-07

申请号：US17814874

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Feng-Cheng Hsu ,  Shuo-Mao Chen

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/13 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/16148 ,  H01L2224/16238

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed over the package substrate and includes a silicon substrate. The interposer substrate has a bottom surface facing and adjacent to the package substrate, a top surface opposite the bottom surface, and a cavity formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the cavity and electrically connected to the first semiconductor device and/or the interposer substrate.

公开(公告)号：US11791301B2

公开(公告)日：2023-10-17

申请号：US17554475

申请日：2021-12-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L24/25 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L21/565 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/1047 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/1431 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure.

公开(公告)号：US11756892B2

公开(公告)日：2023-09-12

申请号：US17121051

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/162 ,  H01L24/13 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16227

Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.

公开(公告)号：US11670577B2

公开(公告)日：2023-06-06

申请号：US17233852

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L25/10 ,  H01L23/053 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

公开(公告)号：US11600597B2

公开(公告)日：2023-03-07

申请号：US17107614

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/108 ,  H01L25/10 ,  H01L23/00 ,  H01L21/78 ,  H01L23/522 ,  H01L23/31

Abstract: The present disclosure provides a semiconductor package, including a substrate, a semiconductor die, and a conductive bump. The substrate has a first surface and a second surface opposite to the first surface. The substrate further includes a conductive line surrounded by a dielectric, and a conductive via connected to the conductive line and protruding from the dielectric at the second surface. The semiconductor die is connected to the first surface of the substrate. The conductive bump is connected to the conductive via at the second surface.

公开(公告)号：US11532569B2

公开(公告)日：2022-12-20

申请号：US16859037

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  De-Dui Marvin Liao

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L25/03 ,  H01L21/683 ,  G06F16/435 ,  G06F16/9535 ,  G06F16/24 ,  G06Q50/00 ,  H01L25/16 ,  H01L25/18 ,  G06Q99/00

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

公开(公告)号：US20220367419A1

公开(公告)日：2022-11-17

申请号：US17874319

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.