公开(公告)号：US12154896B2

公开(公告)日：2024-11-26

申请号：US17460353

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hua Wang ,  Yu-Sheng Lin ,  Chia-Kuei Hsu ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L27/06

Abstract: In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

公开(公告)号：US12132021B2

公开(公告)日：2024-10-29

申请号：US18354668

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L21/76816 ,  H01L23/3107 ,  H01L24/17 ,  H01L24/33 ,  H01L2224/02379 ,  H01L2924/35121

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US12068260B2

公开(公告)日：2024-08-20

申请号：US17462431

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Chen Lee ,  Shu-Shen Yeh ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49833 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/32245

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion integrally formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

公开(公告)号：US20230369246A1

公开(公告)日：2023-11-16

申请号：US18357184

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Po-Yao Lin ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/585 ,  H01L2221/68372

Abstract: A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

公开(公告)号：US20230361070A1

公开(公告)日：2023-11-09

申请号：US18354668

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L21/76816 ,  H01L23/3107 ,  H01L24/17 ,  H01L24/33 ,  H01L2224/02379 ,  H01L2924/35121

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US11784148B2

公开(公告)日：2023-10-10

申请号：US17699196

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L21/76816 ,  H01L23/3107 ,  H01L24/17 ,  H01L24/33 ,  H01L2224/02379 ,  H01L2924/35121

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US20220367419A1

公开(公告)日：2022-11-17

申请号：US17874319

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

公开(公告)号：US20220310503A1

公开(公告)日：2022-09-29

申请号：US17344982

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

公开(公告)号：US20220278037A1

公开(公告)日：2022-09-01

申请号：US17186008

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Tsung-Yen Lee ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has a semiconductor die and a redistribution layer disposed on an active surface of the semiconductor die and electrically connected with the semiconductor die. The redistribution layer has a wiring-free zone arranged at a location below a corner of the semiconductor die. An underfill is disposed between the semiconductor die and the redistribution layer. The wiring-free zone is located below the underfill and is in contact with the underfill. The wiring-free zone extends horizontally from the semiconductor die to the underfill.

公开(公告)号：US20240312887A1

公开(公告)日：2024-09-19

申请号：US18674891

申请日：2024-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/16 ,  H01L2224/16227

Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.