公开(公告)号：US12237277B2

公开(公告)日：2025-02-25

申请号：US18357184

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Po-Yao Lin ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Shin-Puu Jeng

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/58

Abstract: A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

公开(公告)号：US12237276B2

公开(公告)日：2025-02-25

申请号：US18336258

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Chin-Hua Wang ,  Ming-Chih Yew ,  Che-Chia Yang ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

公开(公告)号：US12170238B2

公开(公告)日：2024-12-17

申请号：US18318844

申请日：2023-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L23/29 ,  H01L23/58

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

公开(公告)号：US20240371743A1

公开(公告)日：2024-11-07

申请号：US18777464

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hung Chen ,  Shu-Shen Yeh ,  Yu-Sheng Lin ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/673 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

公开(公告)号：US12125822B2

公开(公告)日：2024-10-22

申请号：US17097059

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Chia Yang ,  Shu-Shen Yeh ,  Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/3185 ,  H01L23/562 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16157

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

公开(公告)号：US20240312852A1

公开(公告)日：2024-09-19

申请号：US18674930

申请日：2024-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Yu-Sheng Lin ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/10 ,  H01L21/4817 ,  H01L23/053 ,  H01L25/0655 ,  H01L23/3128 ,  H01L24/92

Abstract: A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

公开(公告)号：US20240290682A1

公开(公告)日：2024-08-29

申请号：US18658981

申请日：2024-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Yu-Sheng Lin ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L23/24 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/3675 ,  H01L23/24 ,  H01L25/18 ,  H01L25/50

Abstract: Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

公开(公告)号：US12057363B2

公开(公告)日：2024-08-06

申请号：US17462458

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chin-Hua Wang ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/565 ,  H01L23/145 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/35121

Abstract: Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.

公开(公告)号：US12033947B2

公开(公告)日：2024-07-09

申请号：US17231310

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76801 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.

公开(公告)号：US12033928B2

公开(公告)日：2024-07-09

申请号：US18165928

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/16 ,  H01L2224/16227

Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.