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公开(公告)号:US12132021B2
公开(公告)日:2024-10-29
申请号:US18354668
申请日:2023-07-19
发明人: Chia-Kuei Hsu , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/31 , H01L21/56 , H01L21/768 , H01L23/00
CPC分类号: H01L24/09 , H01L21/56 , H01L21/76816 , H01L23/3107 , H01L24/17 , H01L24/33 , H01L2224/02379 , H01L2924/35121
摘要: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
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公开(公告)号:US12100666B2
公开(公告)日:2024-09-24
申请号:US18178775
申请日:2023-03-06
发明人: Shin-Puu Jeng , Techi Wong , Po-Yao Lin , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Chuang
IPC分类号: H01L23/538 , H01L21/48 , H01L21/683 , H01L21/768 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/10
CPC分类号: H01L23/5389 , H01L21/4853 , H01L21/6835 , H01L21/76885 , H01L23/3128 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/24 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2221/68359 , H01L2224/211 , H01L2224/24145 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058
摘要: A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate, forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, forming a conductive pillar electrically connected to the conductive pad, disposing a chip in the substrate layer, and forming a molding layer surrounding the chip.
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公开(公告)号:US20230361070A1
公开(公告)日:2023-11-09
申请号:US18354668
申请日:2023-07-19
发明人: Chia-Kuei Hsu , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/31 , H01L21/56 , H01L23/00 , H01L21/768
CPC分类号: H01L24/09 , H01L21/56 , H01L21/76816 , H01L23/3107 , H01L24/17 , H01L24/33 , H01L2224/02379 , H01L2924/35121
摘要: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
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公开(公告)号:US11784148B2
公开(公告)日:2023-10-10
申请号:US17699196
申请日:2022-03-21
发明人: Chia-Kuei Hsu , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/00 , H01L23/31 , H01L21/56 , H01L21/768
CPC分类号: H01L24/09 , H01L21/56 , H01L21/76816 , H01L23/3107 , H01L24/17 , H01L24/33 , H01L2224/02379 , H01L2924/35121
摘要: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
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公开(公告)号:US20230063251A1
公开(公告)日:2023-03-02
申请号:US17461941
申请日:2021-08-30
发明人: Li-Ling Liao , Ming-Chih Yew , Che-Chia Yang , Po-Chen Lai , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
摘要: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar. The semiconductor device is disposed over the first surface of the redistribution structure, wherein the semiconductor device comprises a third conductive pillar and a fourth conductive pillar, the third conductive pillar is bonded to first conductive pillar through a first joint structure, and the fourth conductive pillar is bonded to second conductive pillar through a second joint structure.
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公开(公告)号:US20220367419A1
公开(公告)日:2022-11-17
申请号:US17874319
申请日:2022-07-27
发明人: Chia-Kuei Hsu , Feng-Cheng Hsu , Ming-Chih Yew , Po-Yao Lin , Shuo-Mao Chen , Shin-Puu Jeng
IPC分类号: H01L25/065 , H01L23/31 , H01L23/538 , H01L21/50 , H01L21/768 , H01L23/00
摘要: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.
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公开(公告)号:US20220310503A1
公开(公告)日:2022-09-29
申请号:US17344982
申请日:2021-06-11
发明人: Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/498 , H01L23/00
摘要: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.
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公开(公告)号:US20220278037A1
公开(公告)日:2022-09-01
申请号:US17186008
申请日:2021-02-26
发明人: Chia-Kuei Hsu , Ming-Chih Yew , Tsung-Yen Lee , Po-Yao Lin , Shin-Puu Jeng
IPC分类号: H01L23/498 , H01L21/48 , H01L21/56 , H01L25/18 , H01L25/00
摘要: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has a semiconductor die and a redistribution layer disposed on an active surface of the semiconductor die and electrically connected with the semiconductor die. The redistribution layer has a wiring-free zone arranged at a location below a corner of the semiconductor die. An underfill is disposed between the semiconductor die and the redistribution layer. The wiring-free zone is located below the underfill and is in contact with the underfill. The wiring-free zone extends horizontally from the semiconductor die to the underfill.
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公开(公告)号:US10797005B2
公开(公告)日:2020-10-06
申请号:US15901355
申请日:2018-02-21
发明人: Chen-Shien Chen , Ming-Da Cheng , Ming-Chih Yew , Yu-Tse Su
IPC分类号: H01L23/00 , H01L23/52 , H01L27/02 , H01L23/538 , H01L23/498 , H01L21/683 , H01L23/31
摘要: A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface of the die, and a molding compound surrounding the die and the warpage control unit. The warpage control unit includes an adhesive portion disposed over the second surface of the die and a warpage adjustable portion sandwiched between the adhesive portion and the die.
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公开(公告)号:US10510734B2
公开(公告)日:2019-12-17
申请号:US16206868
申请日:2018-11-30
发明人: Chen-Shien Chen , Hsiu-Jen Lin , Ming-Chih Yew , Ming-Da Cheng , Yi-Jen Lai , Yu-Tse Su , Sey-Ping Sun , Yang-Che Chen
IPC分类号: H01L21/768 , H01L25/10 , H01L23/498 , H01L23/00 , H01L25/00 , H01L23/31
摘要: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
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