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公开(公告)号:US11329008B2
公开(公告)日:2022-05-10
申请号:US17028862
申请日:2020-09-22
Inventor: Chen-Shien Chen , Ming-Da Cheng , Ming-Chih Yew , Yu-Tse Su
IPC: H01L23/00 , H01L23/52 , H01L27/02 , H01L23/538 , H01L23/498 , H01L21/683 , H01L23/31
Abstract: A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.
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公开(公告)号:US10276548B2
公开(公告)日:2019-04-30
申请号:US15669563
申请日:2017-08-04
Inventor: Chen-Shien Chen , Hsiu-Jen Lin , Ming-Chih Yew , Ming-Da Cheng , Yi-Jen Lai , Yu-Tse Su , Sey-Ping Sun , Yang-Che Chen
Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
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公开(公告)号:US10797005B2
公开(公告)日:2020-10-06
申请号:US15901355
申请日:2018-02-21
Inventor: Chen-Shien Chen , Ming-Da Cheng , Ming-Chih Yew , Yu-Tse Su
IPC: H01L23/00 , H01L23/52 , H01L27/02 , H01L23/538 , H01L23/498 , H01L21/683 , H01L23/31
Abstract: A semiconductor package includes a die including a first surface and a second surface opposite to the first surface, a warpage control unit disposed over the second surface of the die and entirely overlapping the second surface of the die, and a molding compound surrounding the die and the warpage control unit. The warpage control unit includes an adhesive portion disposed over the second surface of the die and a warpage adjustable portion sandwiched between the adhesive portion and the die.
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公开(公告)号:US10510734B2
公开(公告)日:2019-12-17
申请号:US16206868
申请日:2018-11-30
Inventor: Chen-Shien Chen , Hsiu-Jen Lin , Ming-Chih Yew , Ming-Da Cheng , Yi-Jen Lai , Yu-Tse Su , Sey-Ping Sun , Yang-Che Chen
IPC: H01L21/768 , H01L25/10 , H01L23/498 , H01L23/00 , H01L25/00 , H01L23/31
Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
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公开(公告)号:US11908790B2
公开(公告)日:2024-02-20
申请号:US17142809
申请日:2021-01-06
Inventor: Ting-Li Yang , Po-Hao Tsai , Ching-Wen Hsiao , Hong-Seng Shue , Yu-Tse Su
IPC: H01L21/768 , H01L23/522 , H01L23/00 , H01L23/31 , H01L23/495 , H01L23/528 , H01L23/532 , H01L25/065 , H01L21/48
CPC classification number: H01L23/5226 , H01L21/486 , H01L21/4853 , H01L21/76877 , H01L23/528 , H01L24/14
Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.
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公开(公告)号:US20190115326A1
公开(公告)日:2019-04-18
申请号:US16206868
申请日:2018-11-30
Inventor: Chen-Shien Chen , Hsiu-Jen Lin , Ming-Chih Yew , Ming-Da Cheng , Yi-Jen Lai , Yu-Tse Su , Sey-Ping Sun , Yang-Che Chen
IPC: H01L25/10 , H01L23/00 , H01L23/498 , H01L25/00
Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
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公开(公告)号:US20180076184A1
公开(公告)日:2018-03-15
申请号:US15669563
申请日:2017-08-04
Inventor: Chen-Shien Chen , Hsiu-Jen Lin , Ming-Chih Yew , Ming-Da Cheng , Yi-Jen Lai , Yu-Tse Su , Sey-Ping Sun , Yang-Che Chen
IPC: H01L25/10 , H01L25/00 , H01L23/00 , H01L23/498
CPC classification number: H01L25/105 , H01L23/00 , H01L23/31 , H01L23/49816 , H01L24/19 , H01L24/20 , H01L25/50 , H01L2225/1058
Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
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