公开(公告)号：US20240136316A1

公开(公告)日：2024-04-25

申请号：US18402611

申请日：2024-01-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu ,  Ming-Da Cheng ,  Young-Hwa Wu ,  Tao-Sheng Chang

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13017 ,  H01L2224/1355 ,  H01L2224/16059 ,  H01L2924/37001

摘要： A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

公开(公告)号：US20230065429A1

公开(公告)日：2023-03-02

申请号：US17461963

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu

IPC分类号： H01L23/00

摘要： An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.

公开(公告)号：US11342253B2

公开(公告)日：2022-05-24

申请号：US16684774

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10 ,  H01L23/00

摘要： A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US10008479B2

公开(公告)日：2018-06-26

申请号：US15401851

申请日：2017-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Wen Hsiao ,  Chen-Shien Chen ,  Wei Sen Chang ,  Shou-Cheng Hu

IPC分类号： H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L23/50

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

公开(公告)号：US20170372976A1

公开(公告)日：2017-12-28

申请号：US15700830

申请日：2017-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L21/66 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/528

CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

公开(公告)号：US09773749B2

公开(公告)日：2017-09-26

申请号：US15354731

申请日：2016-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo Lung Pan ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/82 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/13 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.

公开(公告)号：US09761503B2

公开(公告)日：2017-09-12

申请号：US14728608

申请日：2015-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hua Chen ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13083 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

公开(公告)号：US20170250139A1

公开(公告)日：2017-08-31

申请号：US15596593

申请日：2017-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Hsien Huang ,  Hsien-Wei Chen ,  Ching-Wen Hsiao ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L23/538 ,  H01L21/78 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31

摘要： A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

公开(公告)号：US20170069594A1

公开(公告)日：2017-03-09

申请号：US15354731

申请日：2016-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo Lung Pan ,  Ching-Wen Hsiao ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/82 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/13 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.

摘要翻译： 提供了使用压缩介电层形成管芯封装以接触和围绕管芯封装中的衬底通孔（TSV）的机构的各种实施例。 压缩介电层减少或消除模具包装的弯曲。 结果，减少或消除由于弯曲引起的破碎再分布层（RDL）的风险。 此外，形成在导电TSV柱和周围的模塑料之间的压电介质层改善了导电TSV柱与模塑料之间的粘合性。 因此，提高了管芯封装的可靠性。

公开(公告)号：US09576821B2

公开(公告)日：2017-02-21

申请号：US14153972

申请日：2014-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sut-I Lo ,  Ching-Wen Hsiao ,  Hsu-Hsien Chen ,  Chen-Shien Chen

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L49/02 ,  H01L23/538 ,  H01L23/64 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L21/56 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00

摘要： A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

摘要翻译： 封装包括管芯，密封剂和电容器。 包装具有包装第一侧和包装第二侧。 模具具有对应于封装第一侧的管芯第一侧，并且具有对应于封装第二侧的管芯第二侧。 模具第一面与模具第二面相对。 密封剂围绕模具。 电容器包括密封剂中的第一板和第二板，并且第一板和第二板的相对表面在从封装第一侧到封装第二侧的方向上延伸。 外部导电连接器附接到封装第一侧和封装第二侧中的至少一个。