公开(公告)号：US20220310543A1

公开(公告)日：2022-09-29

申请号：US17841683

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu ,  Ming-Da Cheng ,  Young-Hwa Wu ,  Tao-Sheng Chang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

公开(公告)号：US10720388B2

公开(公告)日：2020-07-21

申请号：US16192005

申请日：2018-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chiang-Jui Chu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Hung-Yi Kuo

IPC分类号： H01L29/00 ,  H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L21/683

摘要： A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

公开(公告)号：US20170373004A1

公开(公告)日：2017-12-28

申请号：US15700926

申请日：2017-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chiang-Jui Chu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Hung-Yi Kuo

IPC分类号： H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L49/02 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2924/19105

摘要： A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

公开(公告)号：US20240145379A1

公开(公告)日：2024-05-02

申请号：US18173547

申请日：2023-02-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Kun Lai ,  Wei-Hsiang Tu ,  Ching-Ho Cheng ,  Cheng-Nan Lin ,  Chiang-Jui Chu ,  Chien Hao Hsu ,  Kuo-Chin Chang ,  Mirng-Ji Lii

IPC分类号： H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L25/065

CPC分类号： H01L23/5226 ,  H01L23/49816 ,  H01L23/528 ,  H01L25/0657 ,  H01L2225/06544

摘要： Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

公开(公告)号：US10163780B2

公开(公告)日：2018-12-25

申请号：US15700926

申请日：2017-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chiang-Jui Chu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Hung-Yi Kuo

IPC分类号： H01L29/00 ,  H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

摘要： A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

公开(公告)号：US11901323B2

公开(公告)日：2024-02-13

申请号：US17841683

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu ,  Ming-Da Cheng ,  Young-Hwa Wu ,  Tao-Sheng Chang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13017 ,  H01L2224/1355 ,  H01L2224/16059 ,  H01L2924/37001

摘要： A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

公开(公告)号：US20170221819A1

公开(公告)日：2017-08-03

申请号：US15169838

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Hung-Yi Kuo

IPC分类号： H01L23/522 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L49/02 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2924/19105

摘要： A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

公开(公告)号：US20240136316A1

公开(公告)日：2024-04-25

申请号：US18402611

申请日：2024-01-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu ,  Ming-Da Cheng ,  Young-Hwa Wu ,  Tao-Sheng Chang

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13017 ,  H01L2224/1355 ,  H01L2224/16059 ,  H01L2924/37001

摘要： A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

公开(公告)号：US20230065429A1

公开(公告)日：2023-03-02

申请号：US17461963

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu

IPC分类号： H01L23/00

摘要： An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.

公开(公告)号：US20190088595A1

公开(公告)日：2019-03-21

申请号：US16192005

申请日：2018-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chiang-Jui Chu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Hung-Yi Kuo

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48

摘要： A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.