- Patent Title: Chip package with redistribution structure having multiple chips
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Application No.: US17233852Application Date: 2021-04-19
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Publication No.: US11670577B2Publication Date: 2023-06-06
- Inventor: Shin-Puu Jeng , Po-Hao Tsai , Po-Yao Chuang , Feng-Cheng Hsu , Shuo-Mao Chen , Techi Wong
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- The original application number of the division: US15874541 2018.01.18
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00 ; H01L21/52 ; H01L21/56 ; H01L25/10 ; H01L23/053 ; H01L21/683 ; H01L21/48 ; H01L25/00 ; H01L23/31

Abstract:
A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.
Public/Granted literature
- US20210242122A1 CHIP PACKAGE WITH REDISTRIBUTION STRUCTURE Public/Granted day:2021-08-05
Information query
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