公开(公告)号：US09991118B2

公开(公告)日：2018-06-05

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

公开(公告)号：US20180050904A1

公开(公告)日：2018-02-22

申请号：US15543150

申请日：2017-02-07

Applicant: The Curators of the University of Missouri

Inventor： Shubhra GANGOPADHYAY ,  Sangho BOK ,  Samiullah PATHAN ,  Cherian Joseph MATHAI ,  Sagnik BASURAY ,  Keshab GANGOPADHYAY ,  Biyan CHEN ,  Shelia GRANT ,  Aaron WOOD

IPC: B82B3/00 ,  C08J5/00 ,  C01G23/04

CPC classification number: H01L51/5275 ,  B82B3/0038 ,  B82B3/0047 ,  B82Y40/00 ,  C01G23/04 ,  C08J5/005 ,  G02B1/04 ,  G02B1/12 ,  G02B1/14 ,  G02B1/18 ,  G02B5/008 ,  G02B5/18 ,  G02B5/1809 ,  G02B5/1847 ,  G02B5/1852 ,  G02B5/1861 ,  G02B5/1866 ,  G02B5/203 ,  G02B5/3058 ,  G02B27/42 ,  G02B27/4244 ,  G02B27/44 ,  H01L21/02107 ,  H01L21/02109 ,  H01L21/02112 ,  H01L51/52 ,  H01L51/5209 ,  H01L51/5215 ,  H01L51/5218

Abstract: Provided are nanograting structures and methods of fabrication thereof that allow for stable, robust gratings and nanostructure embedded gratings that enhance electromagnetic field, fluorescence, and photothermal coupling through surface plasmon or, photonic resonance. The gratings produced exhibit long term stability of the grating structure and improved shelf life without degradation of the properties such as fluorescence enhancement. Embodiments of the invention build nanograting structures layer-by-layer to optimize structural and optical properties and to enhance durability.

公开(公告)号：US09368407B2

公开(公告)日：2016-06-14

申请号：US14592421

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES U.S. 2 LLC

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Kuen-Ting Shiu

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/7813 ,  H01L21/02109 ,  H01L21/02323 ,  H01L21/306

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

公开(公告)号：US20160155642A1

公开(公告)日：2016-06-02

申请号：US15016999

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Wen Chang ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/423 ,  H01L29/36 ,  H01L29/205 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/792 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02107 ,  H01L21/02109 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/30612 ,  H01L23/485 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L29/20 ,  H01L29/205 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/7783 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

公开(公告)号：US09293357B2

公开(公告)日：2016-03-22

申请号：US13540542

申请日：2012-07-02

Applicant: Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

Inventor： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

IPC: H01L29/49 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3205

CPC classification number: H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

Abstract translation: 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US09269763B2

公开(公告)日：2016-02-23

申请号：US13881420

申请日：2011-11-08

Applicant: Pekka Laukkanen ,  Jouko Lang ,  Marko Punkkinen ,  Marjukka Tuominen ,  Veikko Tuominen ,  Johnny Dahl ,  Juhani Vayrynen

Inventor： Pekka Laukkanen ,  Jouko Lang ,  Marko Punkkinen ,  Marjukka Tuominen ,  Veikko Tuominen ,  Johnny Dahl ,  Juhani Vayrynen

IPC: H01L21/02 ,  H01L29/02 ,  H01L21/28 ,  H01L21/316 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/02 ,  H01L21/02046 ,  H01L21/02109 ,  H01L21/02172 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/31666 ,  H01L21/3245 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205

Abstract: A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

Abstract translation: 一种处理化合物半导体衬底的方法，其中在无定形天然氧化物中清洁含In III-As，III-Sb或III-P衬底的表面的真空条件下的方法，然后将清洁的衬底加热至 温度为约250-550℃，并通过将氧气引入到基底的表面上而被氧化。 本发明还涉及化合物半导体衬底，以及衬底在诸如MOSFET的晶体管的结构中的用途。

公开(公告)号：US09245738B2

公开(公告)日：2016-01-26

申请号：US14091822

申请日：2013-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-chul Jeon ,  Jong-seob Kim ,  Ki-yeol Park ,  Young-hwan Park ,  Jai-kwang Shin ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Hwang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L21/02109 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8613

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a part of the channel supply layer between the source electrode and the drain electrode; a first depletion-forming layer between the gate electrode and the channel supply layer; and a at least one second depletion-forming layer on the channel supply layer between the gate electrode and the drain electrode. The at least one second depletion-forming layer is electrically connected to the source electrode.

Abstract translation: 根据示例性实施例，高电子迁移率晶体管（HEMT）包括沟道层; 通道层上的通道供应层; 在所述沟道层和所述沟道供给层之一上彼此隔开的源电极和漏电极; 源电极和漏电极之间的沟道供给层的一部分上的栅电极; 在栅电极和沟道供应层之间的第一耗尽层; 以及在栅电极和漏电极之间的沟道供应层上的至少一个第二耗尽层。 所述至少一个第二耗尽形成层电连接到所述源电极。

公开(公告)号：US20140342573A1

公开(公告)日：2014-11-20

申请号：US14240897

申请日：2012-08-01

Applicant: Yoshiro Hirose ,  Ryuji Yamamoto

Inventor： Yoshiro Hirose ,  Ryuji Yamamoto

IPC: H01L21/02 ,  C23C16/52 ,  C23C16/30 ,  C23C16/455 ,  H01L21/67 ,  C23C16/36

CPC classification number: H01L21/0214 ,  C23C16/308 ,  C23C16/36 ,  C23C16/401 ,  C23C16/455 ,  C23C16/45531 ,  C23C16/45542 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32541 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/67098 ,  H01L21/67109

Abstract: There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.

Abstract translation: 提供了一种制造半导体器件的方法，包括通过交替执行以下步骤在基片上形成含有特定元素的薄膜并规定次数：形成含有特定元素的第一层，氮， 和碳，通过交替执行预定次数：向基板供给含有特定元素和卤素基团的第一源气体，并向基板供给含有特定元素和氨基的第二源气体， 以及通过将不同于每种源气体的反应气体提供给所述衬底来修饰所述第一层而形成第二层。

公开(公告)号：US20120132982A1

公开(公告)日：2012-05-31

申请号：US13282575

申请日：2011-10-27

Applicant: Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

Inventor： Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

IPC: H01L29/788

CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅极结构的一部分在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

公开(公告)号：US20190148138A1

公开(公告)日：2019-05-16

申请号：US16182325

申请日：2018-11-06

Applicant: NXP USA, INC.

Inventor： JAYNAL A. MOLLA ,  LAKSHMINARAYAN VISWANATHAN ,  GEOFFREY TUCKER

IPC: H01L21/02 ,  H01L23/40 ,  H01L21/60

CPC classification number: H01L21/02109 ,  H01L21/02304 ,  H01L21/02697 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/40 ,  H01L23/427 ,  H01L2021/6027

Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.