公开(公告)号：US08791520B2

公开(公告)日：2014-07-29

申请号：US12986553

申请日：2011-01-07

Applicant: Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

Inventor： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

Abstract translation: 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US09324727B2

公开(公告)日：2016-04-26

申请号：US14176332

申请日：2014-02-10

Applicant: Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

Inventor： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

IPC: H01L27/115 ,  H01L21/762 ,  H01L23/48 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

Abstract: A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

Abstract translation: 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

公开(公告)号：US20090008700A1

公开(公告)日：2009-01-08

申请号：US12137976

申请日：2008-06-12

Applicant: Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

Inventor： Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

IPC: H01L21/28 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract translation: 在制造存储器件的方法中，在衬底上形成隧道绝缘层。 在隧道绝缘层上形成具有基本均匀厚度的浮栅。 在浮栅上形成介电层。 在电介质层上形成控制栅极。 包括浮动栅极的闪速存储器件可具有更均匀的操作特性。

公开(公告)号：US20150146489A1

公开(公告)日：2015-05-28

申请号：US14477513

申请日：2014-09-04

Applicant: Chang-Hyun LEE ,  Albert FAYRUSHIN

Inventor： Chang-Hyun LEE ,  Albert FAYRUSHIN

IPC: G11C16/14 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3459 ,  H01L27/11582

Abstract: In a method of operating a nonvolatile memory device having a substrate and first through n-th word lines stacked in a direction perpendicular to the substrate, first through k-th word line voltages are applied to first through k-th word lines, respectively, which are formed adjacent to the substrate, among the first through n-th word lines. (k+1)-th through n-th word line voltages are applied to (k+1)-th through n-th word lines, respectively, which are formed above the first through k-th word lines, among the first through n-th word lines. An erase voltage, which is higher than the first through n-th word line voltages, is applied to the substrate, where n represents an integer equal to or greater than two, and k represents a positive integer smaller than n. Each of the (k+1)-th through n-th word line voltages is lower than each of the first through k-th word line voltages.

Abstract translation: 在具有基板和在与基板垂直的方向上堆叠的第一至第n字线的非易失性存储器件的操作方法中，第一至第k字线电压分别施加到第一至第k字线， 在第一至第n字线之间形成与基板相邻的第一至第n字线。 第（k + 1）〜第n字线电压分别施加到形成在第一至第k字线之上的第（k + 1）至第n字线， 第n个字线。 将高于第一至第n字线电压的擦除电压施加到衬底，其中n表示等于或大于2的整数，并且k表示小于n的正整数。 第（k + 1）至第n字线电压中的每一个低于第一至第k字线电压中的每一个。

公开(公告)号：US20120132982A1

公开(公告)日：2012-05-31

申请号：US13282575

申请日：2011-10-27

Applicant: Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

Inventor： Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

IPC: H01L29/788

CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅极结构的一部分在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

公开(公告)号：US20100184282A1

公开(公告)日：2010-07-22

申请号：US12752409

申请日：2010-04-01

Applicant: Albert Fayrushin

Inventor： Albert Fayrushin

IPC: H01L21/336

CPC classification number: H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.

Abstract translation: 一种制造半导体存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成初步电荷俘获层，在预充电俘获层上形成蚀刻停止层，其中一部分 初步电荷捕获层不被蚀刻停止层覆盖，去除预电荷捕获层的暴露部分以形成具有均匀厚度的电荷捕获层，在电荷捕获层上形成介电层，并在其上形成栅电极 电介质层。

公开(公告)号：US20140264548A1

公开(公告)日：2014-09-18

申请号：US14176332

申请日：2014-02-10

Applicant: Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

Inventor： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

Abstract: A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

Abstract translation: 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

公开(公告)号：US20110169068A1

公开(公告)日：2011-07-14

申请号：US12986553

申请日：2011-01-07

Applicant: JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

Inventor： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

Abstract translation: 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US07968407B2

公开(公告)日：2011-06-28

申请号：US12752409

申请日：2010-04-01

Applicant: Albert Fayrushin

Inventor： Albert Fayrushin

IPC: H01L21/336

CPC classification number: H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.

Abstract translation: 一种制造半导体存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成初步电荷俘获层，在预充电俘获层上形成蚀刻停止层，其中一部分 初步电荷捕获层不被蚀刻停止层覆盖，去除预电荷捕获层的暴露部分以形成具有均匀厚度的电荷捕获层，在电荷捕获层上形成介电层，并在其上形成栅电极 电介质层。

公开(公告)号：US07842570B2

公开(公告)日：2010-11-30

申请号：US12137976

申请日：2008-06-12

Applicant: Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

Inventor： Albert Fayrushin ,  Byung-Yong Choi ,  Choong-Ho Lee

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract translation: 在制造存储器件的方法中，在衬底上形成隧道绝缘层。 在隧道绝缘层上形成具有基本均匀厚度的浮栅。 在浮栅上形成介电层。 在电介质层上形成控制栅极。 包括浮动栅极的闪速存储器件可具有更均匀的操作特性。