公开(公告)号：US20160351476A1

公开(公告)日：2016-12-01

申请号：US14971750

申请日：2015-12-16

Applicant: STMicroelectronics S.R.L.

Inventor： Fulvio Vittorio FONTANA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/97 ,  H01L2021/6027 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

Abstract translation: 用于制造表面贴装半导体器件的方法，特别是四行无引脚多行类型的方法，包括提供金属引线框架，特别是铜引线框架，其包括多个焊盘，每个焊盘被设计为 接收设备的主体，焊盘通过一行或多行引线接合区域与一行或多行引线接合区域中的最外行一起识别，与最近的行相对应地与相邻焊盘分开， 相邻垫，分离区。

公开(公告)号：US20150206768A1

公开(公告)日：2015-07-23

申请号：US14562381

申请日：2014-12-05

Applicant: Avogy, Inc.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L21/50 ,  H01L23/495 ,  H01L29/20

CPC classification number: H01L21/50 ,  H01L21/8252 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/872 ,  H01L2021/6027 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/206

Abstract: A method of fabricating an electronic package includes providing a package comprising a leadframe and a plurality of pins and providing a gallium nitride (GaN) transistor comprising a drain contact, a source contact, and a gate contact. The method also includes joining the drain contact to the leadframe and providing a GaN diode comprising an anode contact and a cathode contact. The method further includes joining the anode contact to the leadframe.

Abstract translation: 制造电子封装的方法包括提供包括引线框和多个引脚的封装，并提供包括漏极接触，源极接触和栅极接触的氮化镓（GaN）晶体管。 该方法还包括将漏极接触连接到引线框架并提供包括阳极接触和阴极接触的GaN二极管。 该方法还包括将阳极接触件接合到引线框架。

公开(公告)号：US09824956B2

公开(公告)日：2017-11-21

申请号：US14971750

申请日：2015-12-16

Applicant: STMicroelectronics S.R.L.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L21/00 ,  H05K5/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/97 ,  H01L2021/6027 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

公开(公告)号：US08937317B2

公开(公告)日：2015-01-20

申请号：US13730619

申请日：2012-12-28

Applicant: Avogy, Inc.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L31/0256 ,  H01L27/06 ,  H01L23/00 ,  H01L29/872

CPC classification number: H01L21/50 ,  H01L21/8252 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/872 ,  H01L2021/6027 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框，多个引脚，氮化镓（GaN）晶体管和GaN二极管。 GaN晶体管包括漏极区，漂移区，源极区和栅极区; 所述漏极区包括GaN衬底和漏极接触，所述漂移区包括耦合到所述GaN衬底的第一GaN外延层，所述源极区包括源极接触并且通过所述漂移区与所述GaN衬底分离，并且所述栅极区 包括第二GaN外延层和栅极接触。 GaN二极管包括阳极区域和阴极区域，阴极区域包括GaN衬底和阴极接触，并且阳极区域包括耦合到GaN衬底的第三GaN外延层和阳极接触。 漏极触点和阳极触点电连接到引线框架。

公开(公告)号：US20230402294A1

公开(公告)日：2023-12-14

申请号：US18329387

申请日：2023-06-05

Applicant: Skyworks Solutions, Inc.

Inventor： Anthony James LoBianco ,  Ki Wook Lee ,  Yi Liu

IPC: H01L21/56 ,  H01L21/60

CPC classification number: H01L21/565 ,  H01L21/60 ,  H01L2021/6027 ,  H01L2021/6024

Abstract: Methods are disclosed for mounting an electronic package to a circuit board are disclosed. The electronic package can be mounted to the circuit board by use of intermediate solder portions such that each intermediate solder portion couples a corresponding through-mold connection of the electronic package to the circuit board. The through-mold connections can have a melting point in excess of a melting point of the intermediate solder portions. Related electronic packages, electronic assemblies, electronic devices, and methods of manufacturing electronic packages are disclosed.

公开(公告)号：US20140183543A1

公开(公告)日：2014-07-03

申请号：US13730619

申请日：2012-12-28

Applicant: AVOGY, INC.

Inventor： Donald R. Disney ,  Hemal N. Shah

IPC: H01L27/06 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/8252 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/872 ,  H01L2021/6027 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract translation: 电子封装包括引线框，多个引脚，氮化镓（GaN）晶体管和GaN二极管。 GaN晶体管包括漏极区，漂移区，源极区和栅极区; 所述漏极区包括GaN衬底和漏极接触，所述漂移区包括耦合到所述GaN衬底的第一GaN外延层，所述源极区包括源极接触并且通过所述漂移区与所述GaN衬底分离，并且所述栅极区 包括第二GaN外延层和栅极接触。 GaN二极管包括阳极区域和阴极区域，阴极区域包括GaN衬底和阴极接触，并且阳极区域包括耦合到GaN衬底的第三GaN外延层和阳极接触。 漏极触点和阳极触点电连接到引线框架。

公开(公告)号：US11694945B2

公开(公告)日：2023-07-04

申请号：US17301095

申请日：2021-03-24

Applicant: Silanna Asia Pte Ltd

Inventor： Ariel Tan ,  Ren Huei Tzeng

IPC: H01L23/495 ,  H01L23/28 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/4951 ,  H01L21/56 ,  H01L23/28 ,  H01L23/49541 ,  H01L23/49575 ,  H01L2021/6027

Abstract: Disclosed is a device including a first finger of a plurality of lead fingers of a lead frame connected to a first flag. A second finger of the plurality of lead fingers of the lead frame is connected to a second flag. A semiconductor die is coupled to the lead frame. An encapsulant covers the semiconductor die, the lead frame, and a first end of the plurality of lead fingers, and excludes the first flag and the second flag. The first flag and the second flag are separated and electrically isolated from one another by the encapsulant.

公开(公告)号：US20180053710A1

公开(公告)日：2018-02-22

申请号：US15797464

申请日：2017-10-30

Applicant: STMicroelectronics S.R.L.

Inventor： Fulvio Vittorio Fontana

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/97 ,  H01L2021/6027 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

公开(公告)号：US20150054173A1

公开(公告)日：2015-02-26

申请号：US14328672

申请日：2014-07-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hyun KIM ,  Do Jae YOO ,  Heung Woo PARK

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/50 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/142 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L2021/6027 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base substrate; a molding part formed on the base substrate and formed to enclose the first circuit layer and the semiconductor device; a first via formed on the first circuit layer and formed to penetrate through the molding part; and a second circuit layer formed on an upper surface of the molding part and integrally formed with the first via.

Abstract translation: 这里公开了半导体封装，半导体封装的制造方法和堆叠型半导体封装。 根据本发明的优选实施例的半导体封装包括：形成有第一电路层的基底基板; 形成在所述基底基板上的半导体器件; 形成在所述基底基板上并形成为封闭所述第一电路层和所述半导体器件的成型部; 第一通孔，其形成在第一电路层上并形成以穿透模制部件; 以及形成在所述模制部件的上表面上并与所述第一通孔一体形成的第二电路层。

公开(公告)号：US20240282686A1

公开(公告)日：2024-08-22

申请号：US18327220

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  An-Jhih Su ,  Hao-Yi Tsai ,  Tsung-Yuan Yu ,  Po-Yuan Teng ,  Chung-Ming Weng ,  Che-Hsiang Hsu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L23/49827 ,  H01L21/485 ,  H01L21/60 ,  H01L23/49883 ,  H01L2021/6027

Abstract: A method includes forming a first package component and a second package component. The first package component includes a first polymer layer, and a first electrical connector, with at least a part of the first electrical connector being in the first polymer layer. The second package component comprises a second polymer layer, and a second electrical connector, with at least a part of the second electrical connector being in the second polymer layer. The first package component is bonded to the second package component, with the first polymer layer being bonded to the second polymer layer, and the first electrical connector being bonded to the second electrical connector.