公开(公告)号：US20240413012A1

公开(公告)日：2024-12-12

申请号：US18450738

申请日：2023-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  An-Jhih Su ,  Mill-Jer Wang

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.

公开(公告)号：US20240153881A1

公开(公告)日：2024-05-09

申请号：US18402061

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

公开(公告)号：US11587894B2

公开(公告)日：2023-02-21

申请号：US16924216

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Tzuan-Horng Liu ,  Jen-Li Hu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/64

Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.

公开(公告)号：US20210288030A1

公开(公告)日：2021-09-16

申请号：US17334025

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/78 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US20200350221A1

公开(公告)日：2020-11-05

申请号：US16932948

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/66 ,  H01L23/498 ,  G01R1/073 ,  H01L23/522 ,  H01L23/58 ,  H01L21/48

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US10734295B2

公开(公告)日：2020-08-04

申请号：US16148169

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  G01R1/073 ,  H01L23/522 ,  H01L23/58 ,  H01L21/56 ,  H01L21/683

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US11417629B2

公开(公告)日：2022-08-16

申请号：US16787031

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00

Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.

公开(公告)号：US11264362B2

公开(公告)日：2022-03-01

申请号：US16886698

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Nien-Fang Wu ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/304 ,  H01L21/78

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

公开(公告)号：US20210375827A1

公开(公告)日：2021-12-02

申请号：US16886722

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56

Abstract: A package structure includes a first die, a die stack structure, a support structure and an insulation structure. The die stack structure is bonded to the first die. The support structure is disposed on the die stack structure. A width of the support structure is larger than a width of the die stack structure and less than a width of the first die. The insulation structure at least laterally wraps around the die stack structure and the support structure.

公开(公告)号：US20210375826A1

公开(公告)日：2021-12-02

申请号：US16886698

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Nien-Fang Wu ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/78 ,  H01L21/304

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.