公开(公告)号：US12046508B2

公开(公告)日：2024-07-23

申请号：US18108338

申请日：2023-02-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi You ,  He Ren ,  Naomi Yoshida ,  Nikolaos Bekiaris ,  Mehul Naik ,  Martin Jay Seamons ,  Jingmei Liang ,  Mei-Yee Shek

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/76837 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/67103 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/02326

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

公开(公告)号：US12040161B2

公开(公告)日：2024-07-16

申请号：US17477296

申请日：2021-09-16

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Yasutoshi Tsubota ,  Masanori Nakayama ,  Katsunori Funaki ,  Tatsushi Ueda ,  Eiko Takami ,  Yuichiro Takeshima ,  Hiroto Igawa ,  Yuki Yamakado ,  Keita Ichimura

IPC: H05H1/24 ,  H01J37/32 ,  H01L21/02 ,  H01L21/30

CPC classification number: H01J37/3244 ,  H01L21/02252 ,  H01L21/02323 ,  H01L21/3003

Abstract: A method of manufacturing a semiconductor device includes accommodating a substrate in a process chamber; supplying a first gas containing oxygen into the process chamber; generating plasma in the process chamber by exciting the first gas; supplying a second gas containing hydrogen into the process chamber and adjusting a hydrogen concentration distribution in the process chamber according to a density distribution of the plasma in the process chamber; and processing the substrate with oxidizing species generated by the plasma.

公开(公告)号：US20240047198A1

公开(公告)日：2024-02-08

申请号：US18227016

申请日：2023-07-27

Applicant: ASM IP Holding B.V.

Inventor： Hirotsugu Sugiura ,  Yoshiyuki Kikuchi

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/32 ,  C23C16/56 ,  C23C16/505

CPC classification number: H01L21/02323 ,  H01L21/02126 ,  H01L21/0234 ,  H01L21/02274 ,  H01L21/0228 ,  H01J37/3244 ,  H01J37/32091 ,  H01J37/32146 ,  C23C16/325 ,  C23C16/56 ,  C23C16/505 ,  H01L21/02167 ,  H01J2237/332

Abstract: Methods and systems of forming treated silicon-carbon material are disclosed. Exemplary methods include depositing silicon-carbon material onto a surface of the substrate and treating the silicon-carbon material. The step of treating can include a first treatment step followed by a second treatment step, wherein the first treatment step includes providing first reductant gas activated species and the second treatment step includes providing one or more of a first oxidant gas activated species and a second reductant gas activated species.

公开(公告)号：US20230377944A1

公开(公告)日：2023-11-23

申请号：US18362302

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yun Peng

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L29/0649 ,  H01L27/0886 ,  H01L21/823481 ,  H01L21/0228 ,  H01L21/02126 ,  H01L21/823431 ,  H01L21/02323

Abstract: Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.

公开(公告)号：US20190088487A1

公开(公告)日：2019-03-21

申请号：US16058310

申请日：2018-08-08

Applicant: Cypress Semiconductor Corporation

Inventor： Krishnaswamy Ramkumar ,  Igor Kouznetsov ,  Venkatraman Prabhakar ,  Ali Keshavarzi

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11573 ,  H01L27/11568

CPC classification number: H01L29/40117 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02323 ,  H01L21/02337 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

公开(公告)号：US20190013406A1

公开(公告)日：2019-01-10

申请号：US16040053

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： Sameer Pradhan ,  Jeanne Luce

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/7851 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

公开(公告)号：US20180337258A1

公开(公告)日：2018-11-22

申请号：US15900537

申请日：2018-02-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02323 ,  H01L21/823487 ,  H01L27/10873 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/66545

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming spaced lower conductive lines over a substrate. A gate insulator is formed in openings that are individually directly above individual of the lower conductive lines. The openings are formed into laterally-spaced lines comprising sacrificial material and are spaced longitudinally there-along. Channel material is formed in the individual openings laterally adjacent the gate insulator and is electrically coupled to the individual lower conductive line there-below. The sacrificial material is replaced with conductive-gate material. Other methods are disclosed including arrays of elevationally-extending transistors independent of method of manufacture.

公开(公告)号：US20180254291A1

公开(公告)日：2018-09-06

申请号：US15966231

申请日：2018-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US10056488B2

公开(公告)日：2018-08-21

申请号：US15400958

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Sameer Pradhan ,  Jeanne Luce

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

公开(公告)号：US20180212018A1

公开(公告)日：2018-07-26

申请号：US15926214

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Paul C. Jamison ,  John Rozen

IPC: H01L49/02 ,  H01L21/02

CPC classification number: H01L28/75 ,  H01L21/02186 ,  H01L21/02244 ,  H01L21/02323

Abstract: Capacitors and methods of forming the same include forming an oxygenated dielectric layer on a first conductive layer. A second conductive layer is formed on the oxygenated dielectric layer. The oxygenated dielectric layer is heated to release the oxygen from the oxygenated dielectric layer and to oxidize the first and second conductive layers at interfaces between the dielectric layer and the first and second conductive layers, forming barrier layers at the interfaces.