公开(公告)号：US20240282827A1

公开(公告)日：2024-08-22

申请号：US18172916

申请日：2023-02-22

Applicant: GAN SYSTEMS INC.

Inventor： Marco A. ZUNIGA ,  Thomas William MACELWEE ,  Rohan SAMSI ,  Lucas Andrew Milner ,  Vineet Unni ,  Jayasimha S. PRASAD ,  Ashutosh Ravindra JOHARAPURKAR ,  Ramesh G. KARPUR

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/7786

Abstract: The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.

公开(公告)号：US11935943B2

公开(公告)日：2024-03-19

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan Yu ,  Seung Hun Lee ,  Yang Xu

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/20 ,  H01L29/201 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20230395707A1

公开(公告)日：2023-12-07

申请号：US18455136

申请日：2023-08-24

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Simon FICHTNER ,  Fabian LOFINK ,  Bernhard WAGNER ,  Holger KAPELS

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41766

Abstract: An electronic component comprises a first layer and a second layer, wherein a main surface of the first layer is arranged opposite a main surface of the second layer. The first layer comprises a polarized first material. A polarization of the first material faces in a first direction. The second layer comprises a polarized second material having at least one polarization state, wherein a direction of a polarization of the second material at least in the one polarization state of the second material is at least in part opposite to the first direction such that a charge zone forms along the main surface of the first and/or the second layer, said charge zone being electrically conductive at least when the second material is in the one polarization state.

公开(公告)号：US20190245074A1

公开(公告)日：2019-08-08

申请号：US16390543

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YAO-CHUNG CHANG ,  PO-CHIH CHEN ,  JIUN-LEI JERRY YU ,  CHUN LIN TSAI

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/66 ,  H01L21/324 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7787

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

公开(公告)号：US20190006502A1

公开(公告)日：2019-01-03

申请号：US16125733

申请日：2018-09-09

Applicant: Robert L. Coffie

Inventor： Robert L. Coffie

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201 ,  H01L29/66 ,  H01L29/267 ,  H01L29/24

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7787

Abstract: A transistor structure including a scandium gallium nitride back-barrier layer. For instance, the transistor structure may include a buffer layer disposed on a substrate and a back-barrier layer disposed on the buffer layer, the back-barrier layer including scandium gallium nitride (ScxGa1-xN). The transistor structure may further include a channel layer disposed on the back-barrier layer, and a barrier layer disposed on the channel layer. The barrier layer may include at least one of aluminum gallium nitride, indium gallium aluminum nitride, scandium aluminum nitride, scandium aluminum gallium nitride, or indium gallium boron aluminum nitride. The transistor structure may be incorporated into a high electron mobility transistor (HEMT).

公开(公告)号：US10038305B2

公开(公告)日：2018-07-31

申请号：US15460828

申请日：2017-03-16

Applicant: FUJI XEROX CO., LTD.

Inventor： Takashi Kondo

IPC: G03G15/04 ,  H01L27/15 ,  H01S5/22 ,  H01L29/74 ,  H01L33/06 ,  H01L33/14 ,  H01L33/30 ,  H01L33/10 ,  H01L29/8605 ,  H01S5/026 ,  H01S5/30 ,  H01L29/201 ,  H01S5/042 ,  H01S5/183 ,  H01S5/32 ,  H01S5/40 ,  H01S5/42

CPC classification number: H01S5/2205 ,  G03G15/04054 ,  H01L27/15 ,  H01L27/153 ,  H01L29/201 ,  H01L29/74 ,  H01L29/8605 ,  H01L33/06 ,  H01L33/105 ,  H01L33/145 ,  H01L33/30 ,  H01S5/0261 ,  H01S5/0427 ,  H01S5/18308 ,  H01S5/2222 ,  H01S5/3095 ,  H01S5/3216 ,  H01S5/4031 ,  H01S5/423

Abstract: A light emitting component includes plural transfer elements, plural setting thyristors, and plural light emitting elements. The transfer elements are configured to be sequentially brought into an ON state. The setting thyristors are connected to the transfer elements, respectively. The setting thyristors are configured to be brought into a state where the setting thyristors are capable of changing to the ON state when the transfer elements are brought into the ON state. The light emitting elements are stacked on the setting thyristors through tunnel junctions, respectively. The light emitting elements are configured to emit light of increase a light emission amount when the setting thyristors are brought into the ON state.

公开(公告)号：US10014403B2

公开(公告)日：2018-07-03

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L21/027 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

公开(公告)号：US10008580B2

公开(公告)日：2018-06-26

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1-xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1-xA, wherein x is not 0.53.

公开(公告)号：US09997667B2

公开(公告)日：2018-06-12

申请号：US15495169

申请日：2017-04-24

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Remigijus Gaska ,  Jinwei Yang ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/14

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/15 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/207 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L33/325 ,  H01S5/2009 ,  H01S5/3211 ,  H01S5/3216 ,  H01S5/3407 ,  H01S5/34333

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

公开(公告)号：US09960265B1

公开(公告)日：2018-05-01

申请号：US15422764

申请日：2017-02-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek Banerjee ,  Peter Moens ,  Gordon M. Grivna

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/02175 ,  H01L21/02107 ,  H01L21/02241 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66462 ,  H01L29/7786

Abstract: In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.