公开(公告)号：US11983622B2

公开(公告)日：2024-05-14

申请号：US18111471

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US20220139835A1

公开(公告)日：2022-05-05

申请号：US17574073

申请日：2022-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang-ill Seo ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06

Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.

公开(公告)号：US20210376109A1

公开(公告)日：2021-12-02

申请号：US17396385

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28 ,  H01L27/092

Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

公开(公告)号：US20210265334A1

公开(公告)日：2021-08-26

申请号：US16853535

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  G06F30/392

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US10971420B2

公开(公告)日：2021-04-06

申请号：US16374524

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

公开(公告)号：US20200135735A1

公开(公告)日：2020-04-30

申请号：US16298887

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

公开(公告)号：US20190385856A1

公开(公告)日：2019-12-19

申请号：US16551028

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US10381271B2

公开(公告)日：2019-08-13

申请号：US15997596

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L27/04 ,  H01L21/84

Abstract: A field effect transistor includes a fin having a stack of nanowire-like channel regions including at least first and a second nanowire-like channel regions, source and drain electrodes on opposite sides of the fin, a dielectric separation region including a dielectric material between the first and second nanowire-like channel regions, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions.

公开(公告)号：US10199474B2

公开(公告)日：2019-02-05

申请号：US15485188

申请日：2017-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.

公开(公告)号：US20180166550A1

公开(公告)日：2018-06-14

申请号：US15485188

申请日：2017-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L2029/42388

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.