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公开(公告)号：US20210376109A1
公开(公告)日：2021-12-02
申请号：US17396385
申请日：2021-08-06
发明人： Wei-E Wang , Mark S. Rodder
IPC分类号： H01L29/51 , H01L21/8238 , H01L29/04 , H01L29/06 , H01L29/161 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/28 , H01L27/092
摘要： A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.
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公开(公告)号：US10971420B2
公开(公告)日：2021-04-06
申请号：US16374524
申请日：2019-04-03
发明人： Wei-E Wang , Mark S. Rodder , Vassilios Gerousis
IPC分类号： H01L23/367 , H01L23/373 , H01L23/522 , H01L25/065 , H01L27/06
摘要： A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.
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公开(公告)号：US20190385856A1
公开(公告)日：2019-12-19
申请号：US16551028
申请日：2019-08-26
发明人： Wei-E Wang , Mark S. Rodder , Borna J. Obradovic
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8238 , H01L27/092
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
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公开(公告)号：US09812449B2
公开(公告)日：2017-11-07
申请号：US15158459
申请日：2016-05-18
发明人： Borna J. Obradovic , Titash Rakshit , Mark S. Rodder , Wei-E Wang
IPC分类号： H01L21/02 , H01L27/088 , H01L29/06 , H01L29/20 , H01L29/423 , H01L29/49
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/8252 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/201 , H01L29/4232 , H01L29/42392 , H01L29/4916 , H01L29/4966 , H01L29/775 , H01L29/778
摘要： A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.
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公开(公告)号：US20170148787A1
公开(公告)日：2017-05-25
申请号：US15158459
申请日：2016-05-18
发明人： Borna J. Obradovic , Titash Rakshit , Mark S. Rodder , Wei-E Wang
IPC分类号： H01L27/088 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/20
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/8252 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/201 , H01L29/4232 , H01L29/42392 , H01L29/4916 , H01L29/4966 , H01L29/775 , H01L29/778
摘要： A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.
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公开(公告)号：US20160042956A1
公开(公告)日：2016-02-11
申请号：US14666770
申请日：2015-03-24
发明人： Jorge A. Kittl , Mark S. Rodder , Wei-E Wang
IPC分类号： H01L21/28 , H01L29/51 , H01L29/778
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28194 , H01L29/517 , H01L29/778
摘要： Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment that mixes with and penetrates the first dielectric layer and reacts with the semiconductor body to form a new interface layer; and performing gate stack processing, including deposition of a gate electrode.
摘要翻译： 示例性实施例提供使用O3后处理来制造具有用于栅极堆叠的界面层的场效应晶体管（FET）。 示例性实施例的方面包括：在衬底上形成半导体本体; 清洁半导体体的表面; 在所述半导体主体上沉积第一电介质层; 执行与第一电介质层混合并渗透第一电介质层并与半导体本体反应以形成新界面层的O3处理; 以及执行栅堆叠处理，包括沉积栅电极。
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公开(公告)号：US11476121B2
公开(公告)日：2022-10-18
申请号：US16551028
申请日：2019-08-26
发明人： Wei-E Wang , Mark S. Rodder , Borna J. Obradovic
IPC分类号： H01L21/28 , H01L27/092 , H01L21/8238 , H01L29/51 , H01L21/8234 , H01L27/088 , H01L29/49
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
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公开(公告)号：US11069576B2
公开(公告)日：2021-07-20
申请号：US16942762
申请日：2020-07-29
发明人： Wei-E Wang
IPC分类号： H01L21/8234 , H01L21/28 , H01L29/51 , H01L29/49 , H01L27/088
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
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公开(公告)号：US10770353B2
公开(公告)日：2020-09-08
申请号：US15898421
申请日：2018-02-16
发明人： Wei-E Wang
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/51 , H01L29/49
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
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10.发明申请公开(公告)号：US20190148237A1
公开(公告)日：2019-05-16
申请号：US15898421
申请日：2018-02-16
发明人： Wei-E Wang
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/51 , H01L29/49 , H01L21/28
摘要： A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
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