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    Method for synthesis of graphene and other carbon nanomaterials on a ferromagnetic substrate in the ambient atmosphere
    5.
    发明公开
    Method for synthesis of graphene and other carbon nanomaterials on a ferromagnetic substrate in the ambient atmosphere 审中-公开

    公开(公告)号：US20240327974A1

    公开(公告)日：2024-10-03

    申请号：US18260785

    申请日：2022-01-18

    申请人： Viesturs Kalnins

    发明人： Viesturs Kalnins

    IPC分类号： C23C16/26 ,  C01B32/186 ,  C23C16/46

    CPC分类号： C23C16/26 ,  C01B32/186 ,  C23C16/463

    摘要： The presented invention relates to the graphene and other carbon nanomaterial synthesis which requires a metal substrate-catalyst, elevated temperature and carbon precursors. The method for the synthesis of graphene and other carbon nanomaterials on a ferromagnetic substrate in the ambient atmosphere includes the following steps: 1) a ferromagnetic substrate is introduced in a closed chamber in the ambient atmosphere: 2) a carbon precursor is introduced in the same chamber: 3) the substrate is heated by electromagnetic induction 4) the carbon precursor is evaporated and/or thermally decomposed: 5) produced gases come into contact with the hot substrate: 6) the substrate is rapidly cooled. In addition, the carbon precursor is ignited, or the combustion and evaporation and/or thermal decomposition are performed separately by using the same or two different carbon precursors.

    Method of making graphene structures and devices
    7.
    发明授权
    Method of making graphene structures and devices 有权

    公开(公告)号：US12084758B2

    公开(公告)日：2024-09-10

    申请号：US17625016

    申请日：2020-07-07

    申请人： PARAGRAF LIMITED

    发明人： Hugh Glass ,  Ivor Guiney ,  Martin Tyler ,  Robert Wallis ,  Rosie Baines ,  Simon Thomas

    IPC分类号： C01B32/186 ,  B23K26/402 ,  C23C16/26 ,  C23C16/46 ,  C23C16/56 ,  G01R33/00 ,  G01R33/07 ,  B23K101/40

    CPC分类号： C23C16/26 ,  B23K26/402 ,  C23C16/46 ,  C23C16/56 ,  G01R33/0052 ,  G01R33/07 ,  B23K2101/40

    摘要： The present invention provides a method for the production of an electronic device, the method comprising: (i) providing a substrate comprising first and second layers on a heated susceptor in a reaction chamber, the chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the substrate and have a constant separation from the substrate, (ii) supplying a flow comprising a precursor compound through the inlets and into the reaction chamber to thereby decompose the precursor compound and form a graphene layer structure on a surface of the first layer of the substrate, wherein the inlets are cooled to less than 100° C. and the susceptor is heated to a temperature of at least 50° C. in excess of a decomposition temperature of the precursor, (iii) selectively laser ablating the graphene to expose one or more portions of the surface of the first layer of the substrate, and (iv) selectively laser ablating the surface of the first layer of the substrate to expose one or more portions of the second layer of the substrate, wherein the first layer is an electrically conductive layer and the second layer is an electrically insulative layer, or wherein the second layer is an electrically conductive layer and the first layer is an electrically insulative layer.

    SUPPORTS FOR SEMICONDUCTOR STRUCTURES
    8.
    发明公开
    SUPPORTS FOR SEMICONDUCTOR STRUCTURES 审中-公开

    公开(公告)号：US20240290615A1

    公开(公告)日：2024-08-29

    申请号：US18647252

    申请日：2024-04-26

    申请人： Soitec

    发明人： Young-Pil Kim

    IPC分类号： H01L21/02 ,  C23C16/24 ,  C23C16/26 ,  C23C16/44

    CPC分类号： H01L21/02658 ,  C23C16/24 ,  C23C16/26 ,  C23C16/4404 ,  C23C16/4405 ,  H01L21/02238

    摘要： A support for a semiconductor structure comprises a base substrate and a charge trapping layer on the base substrate. The charge trapping layer comprises an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer. The charge trapping material has a grain size between 100 nanometers (nm) and 1000 nm, and/or a lattice parameter greater than a lattice parameter of the at least one interlayer. Also disclosed is a semiconductor structure comprising such support.