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公开(公告)号：US20240321854A1
公开(公告)日：2024-09-26
申请号：US18731910
申请日：2024-06-03
发明人： Maohua DU
CPC分类号： H01L25/18 , H01L21/568 , H01L23/293 , H01L23/3135 , H01L23/481 , H01L24/08 , H01L24/32 , H01L24/80 , H01L2224/08145 , H01L2224/32145 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2225/06544 , H01L2225/06548 , H01L2225/06586 , H01L2924/1815
摘要： A fan-out packaging method and packaging structure are provided. The method includes: fixing a first chip in a groove of a dummy chip; bonding a plurality of second chips with the dummy chip and the first chip respectively; forming a first plastic encapsulation layer to wrap the plurality of second chips; forming a second plastic encapsulation layer to wrap the first chip, the dummy chip, and the first plastic encapsulation layer; and forming a redistribution wiring layer on surfaces of the dummy chip and the first chip away from the plurality of second chip.
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公开(公告)号：US20240321821A1
公开(公告)日：2024-09-26
申请号：US18731884
申请日：2024-06-03
发明人： Maohua DU
CPC分类号： H01L24/80 , H01L23/3107 , H01L23/481 , H01L24/08 , H01L25/16 , H10B80/00 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
摘要： A packaging method and a packaging structure of a multi-layer stacked memory are provided. The packaging method includes providing a buffer chip, a plurality of dummy chips and a plurality of first memory chips. The dummy chip is provided with a groove body, the buffer chip is provided with a plurality of first conductive vias, and the plurality of first memory chips are provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias. The packaging method also includes respectively fixing each of the plurality of first memory chips in the groove body of the dummy chip to form a plurality of micro-memory modules; and sequentially hybrid-bonding and stacking the plurality of the micro-memory modules on the buffer chip. An orthographic projection of a micro-memory module of the plurality of micro-memory modules on the buffer chip coincides with the buffer chip.
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公开(公告)号：US20240321825A1
公开(公告)日：2024-09-26
申请号：US18680211
申请日：2024-05-31
发明人： Maohua DU
CPC分类号： H01L24/96 , H01L21/561 , H01L23/28 , H01L24/19 , H01L24/20 , H01L2224/19 , H01L2224/214 , H01L2224/96
摘要： A fan-out packaging method and packaging structure are provided. The method includes: providing a wafer carrier, a panel carrier, and groups of first chips; fixing first surfaces of the groups of first chips on the wafer carrier; forming a first plastic encapsulation layer on second surfaces of the groups of first chips; separating the groups of first chips from the wafer carrier; forming a high-density interconnection wiring layer on the first surfaces of the groups of first chips; cutting the groups of first chips; fixing one side of the groups of first chips with the high-density interconnection wiring layer on the panel carrier; forming a second plastic encapsulation layer on another side of the groups of first chips away from the high-density interconnection wiring layer; separating the groups of first chips from the panel carrier; and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
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公开(公告)号：US20240321853A1
公开(公告)日：2024-09-26
申请号：US18680321
申请日：2024-05-31
发明人： Maohua DU
CPC分类号： H01L25/18 , H01L21/56 , H01L23/293 , H01L23/3135 , H01L23/481 , H01L24/08 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/08145 , H01L2224/08225 , H01L2224/13111 , H01L2224/14051 , H01L2224/16145 , H01L2224/16225 , H01L2224/81012 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06548 , H01L2924/1434 , H01L2924/1436
摘要： A packaging method and a packaging structure of a multi-layer stacked high-bandwidth memory are provided. The packaging method includes respectively providing a substrate and a plurality of memory chips. The packaging method also includes sequentially forming a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface of the memory chip; and forming a plurality of pads on a second surface of the memory chip. In addition, the packaging method includes nesting a second conductive bump and a pad on every adjacent two memory chips through a thermal compression bonding process, to insulate and sequentially stack the plurality of memory chips over the substrate. Further, the method includes performing a reflow soldering process on the plurality of stacked memory chips and the substrate; and forming a plastic encapsulation layer to wrap the plurality of memory chips and the substrate.
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公开(公告)号：US20240321704A1
公开(公告)日：2024-09-26
申请号：US18680282
申请日：2024-05-31
发明人： Maohua DU
IPC分类号： H01L23/498 , H01L21/603 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/49822 , H01L21/603 , H01L23/3128 , H01L23/49816 , H01L24/08 , H01L24/48 , H01L25/0657 , H01L2224/08145 , H01L2224/08225 , H01L2224/48147 , H01L2224/48227 , H01L2225/06506 , H01L2225/0651 , H01L2924/15172 , H01L2924/15311 , H01L2924/182
摘要： A fan-out packaging method and packaging structure are provided. The method includes: fixing a first chip in a groove of a dummy chip where the first chip and the dummy chip are provided with a plurality of conductive through holes; bonding the second chip with the dummy chip and the first chip respectively; forming a plastic encapsulation layer to wrap the first chip, the dummy chip and the second chip; and forming a redistribution wiring layer on surfaces of the dummy chip and the first chip away from the second chip. The redistribution layer is electrically connected to the first chip through the plurality of conductive through holes.
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