公开(公告)号：US20240389308A1

公开(公告)日：2024-11-21

申请号：US18589891

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Seokhan Park ,  Iljae Shin ,  Kiseok Lee ,  Sanghyun Lee

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a memory cell array region, a contact region, and a connection region, gate electrodes on the memory cell array region and the connection region, and stacked in a vertical direction, active layers on the memory cell array region and stacked in the vertical direction, and conductive connection patterns on the connection region and the contact region, and stacked in the vertical direction, wherein each of the active layers includes a channel region vertically overlapping the gate electrodes, the gate electrodes are electrically connected to the conductive connection patterns, the conductive connection patterns have a step structure including step regions spaced apart from each other, and the step structure has a first step portion stepping down along a first direction and a second step portion facing the first step portion and stepping up along the first direction.

公开(公告)号：US20250133728A1

公开(公告)日：2025-04-24

申请号：US18825982

申请日：2024-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Iljae Shin ,  Jinwoo Han ,  Seokhan Park ,  Sungmin Park ,  Gyuhwan Oh ,  Kiseok Lee

IPC: H10B12/00 ,  H01L29/45

Abstract: A semiconductor device includes a bit line, a channel, a word line and a capacitor. The bit line is disposed on a substrate, and extends in a first direction substantially perpendicular to an upper surface of the substrate. The channel at least partially surrounds a sidewall of the bit line. The word line is disposed on the substrate, and at least a portion of the word line overlaps the channel in a horizontal direction substantially parallel to the upper surface of the substrate. The capacitor is electrically connected to the channel, and at least a portion of the capacitor overlaps the channel and the word line in the horizontal direction.

公开(公告)号：US11502084B2

公开(公告)日：2022-11-15

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.