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1.发明公开公开(公告)号：US20240186319A1
公开(公告)日：2024-06-06
申请号：US17784707
申请日：2021-08-06
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
Inventor： Wenyu HUA , Zhongwei LUO , Zhi ZHANG
IPC: H01L27/088 , H10B12/00
CPC classification number: H01L27/088 , H10B12/05 , H10B12/33 , H10B12/482
Abstract: The disclosure provides a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor array may include the following operations. A wafer is provided. The wafer is partially etched from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array, here the transistor pillar array includes multiple transistor pillars arranged in an array, each of the multiple transistor pillars is located at a corresponding grid point of the grid-like etched trench and has a first preset thickness smaller than an initial thickness of the wafer; and the first direction is a thickness direction of the wafer and is perpendicular to the first surface. An insulating material is deposited in the grid-like etched trench to form an insulating layer.
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2.发明公开公开(公告)号：US20240179922A1
公开(公告)日：2024-05-30
申请号：US17782868
申请日：2021-08-06
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
Inventor： Wenyu HUA , Xilong WANG
Abstract: Embodiments provide a transistor and a method for manufacturing same, a semiconductor device and a method for manufacturing same. The method for manufacturing a transistor includes operations. A wafer is provided, the wafer has multiple transistor formation regions, each of which has a transistor pillar with an exposed gate formation surface. A gate oxide layer and a gate are sequentially formed on the gate formation surface of each of the transistor pillars. A source is formed at a first end of each of the transistor pillars. A drain is formed at a second end of each of the transistor pillars, here the first end and the second end are opposite ends of each of the transistor pillars in a first direction which is a thickness direction of the wafer; a part of each of the transistor pillars between the source and the drain forms a channel region of the transistor.
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公开(公告)号：US20250016989A1
公开(公告)日：2025-01-09
申请号：US18577386
申请日：2022-03-07
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
IPC: H10B12/00
Abstract: Disclosed are a semiconductor structure and a manufacturing method which includes providing a substrate; forming a first recessed area from a first surface of the substrate, wherein at least two protruding structures are reserved in the first recessed area, and there are at least some of non-overlapping areas in the projections of any two adjacent protruding structures in the direction perpendicular to the extending direction of the protruding structures; filling the first recessed area with an insulating material; thinning from a second surface of the substrate until the insulating material is exposed to the second surface protruding structures from the second surface to form a second recessed area; filling the second recessed area with a conductive material to form bit lines; and at surface positions of the bit lines corresponding to the non-overlapping areas, forming bit line lead-out structures.
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公开(公告)号：US20240341085A1
公开(公告)日：2024-10-10
申请号：US18575998
申请日：2022-02-07
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
IPC: H10B12/00
CPC classification number: H10B12/482 , H10B12/05 , H10B12/33
Abstract: A semiconductor structure and a manufacturing method include providing a substrate with a first surface and a second surface, which are opposite each other; from the first surface of the substrate, forming a transistor array having a plurality of transistors; thinning the substrate from the second surface until a first end of a conductive channel of each transistor is exposed, wherein the first end is the end of the conductive channel that is close to the second surface; forming an insulating layer, which covers at least part of the first end of the conductive channel, such that a first width of the exposed first end of the conductive channel is less than a second width of the conductive channel; and forming a bit line structure, which covers the exposed part of the first end of the conductive channel.
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公开(公告)号：US20240196588A1
公开(公告)日：2024-06-13
申请号：US18554367
申请日：2021-08-30
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
IPC: H10B12/00
CPC classification number: H10B12/0335 , H10B12/053 , H10B12/315 , H10B12/34 , H10B12/482 , H10B12/488
Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first surface and a second surface, which includes a plurality of active areas arranged along a first direction and in parallel along a second direction; a plurality of first recesses arranged in the substrate; a word line gate structure disposed in a first recess, which includes a first side wall and a second side wall, wherein the second side wall is adjacent to an active area; a first isolation structure disposed in the first recess and disposed between the word line gate structure and an active area; a plurality of capacitor structures disposed on the first surface and electrically coupled with an active area; and a plurality of bit lines disposed on the second surface, which are arranged along the first direction and parallel to the second direction.
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Patent Agency Ranking
公开(公告)号：US20250071978A1
公开(公告)日：2025-02-27
申请号：US18726800
申请日：2022-05-30
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
Inventor： Fandong LIU , Wenyu HUA , Shengqi CUI , Wenxiang XU , Dongmen SONG
IPC: H10B12/00
Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes: a substrate including active areas and isolation regions; a plurality of first recesses disposed in the substrate; a first word line gate structure, a second word line gate structure, a first connection gate and a second connection gate disposed on side surfaces of a first recess; a dielectric layer disposed in the first recess; a second recess and a third recess disposed in the dielectric layer in the isolation regions, central axes of the third recess and the second recess doing not overlap along the second direction; a first isolation structure disposed in the second recess; a second isolation structure disposed in the third recess; a first connection plate disposed on the second connection gate; and a second connection plate disposed on the first connection gate.
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公开(公告)号：US20240292606A1
公开(公告)日：2024-08-29
申请号：US18574057
申请日：2021-09-02
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
Inventor： Wenyu HUA , Fandong LIU , Xiao DING
IPC: H10B12/00
CPC classification number: H10B12/488 , H10B12/038 , H10B12/315 , H10B12/482
Abstract: A semiconductor structure and a formation method therefor. The semiconductor structure comprises: a substrate, which has opposite first and second surfaces, and comprises several discrete active areas arranged in a first direction and parallel to a second direction, wherein the first direction is perpendicular to the second direction; word line gate structures, which are disposed in the active areas, extend from the first surface to the second surface, are arranged in the second direction, and run through the active areas along the first direction; a first isolation structure, which is disposed in the substrate and extends from the second surface to the first surface; bit line structures, which are disposed on the first surface, electrically coupled with the active areas, arranged in the first direction, and parallel to the second direction; and capacitor structures, which are disposed on the second surface and electrically coupled with the active areas.
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公开(公告)号：US20240244833A1
公开(公告)日：2024-07-18
申请号：US18552837
申请日：2021-09-02
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
IPC: H10B12/00 , H01L21/302 , H01L23/14 , H01L29/06
CPC classification number: H10B12/488 , H01L21/302 , H01L23/145 , H01L29/0653 , H10B12/02 , H10B12/482
Abstract: A dynamic random access memory and a forming method therefor. The dynamic random access memory comprises: a substrate (100), which has opposite first surface (101) and second surface (102), and comprises several active regions (103), and each active region (103) comprises an isolation region (104), a channel region (105) and a word line region (106); a first isolation layer (108), which is located in the isolation region (104); a word line gate structure (111), which is located in the word line region (106); a first source/drain dope region (112), which is located in the channel region (105) on the first surface (101); a bit line layer (114) which is located on the first surface (101); a second source/drain dope region (116) which is located in the channel region (105) on the second surface (102); and several capacitor structures (119), which are located on the second surface (102).
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公开(公告)号：US20240188276A1
公开(公告)日：2024-06-06
申请号：US17782791
申请日：2021-08-06
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
Inventor： Wenyu HUA , Fandong LIU , Xiao DING
IPC: H10B12/00 , G11C11/4091
CPC classification number: H10B12/09 , H10B12/315 , H10B12/50 , G11C11/4091
Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.
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公开(公告)号：US20240172418A1
公开(公告)日：2024-05-23
申请号：US18552391
申请日：2022-01-10
Applicant: ICLEAGUE TECHNOLOGY CO., LTD.
IPC: H10B12/00
CPC classification number: H10B12/33 , H10B12/036 , H10B12/053
Abstract: A semiconductor structure and a forming method therefor. The forming method comprises: providing a first substrate, which has opposite first and second faces, and comprises several discrete active regions arranged in a first direction and parallel to a second direction that is perpendicular to the first direction, wherein the first face exposes an isolation layer disposed between adjacent active regions; forming in the first substrate several first recesses, which extend from the first face to the second face, are arranged in the second direction, and penetrates the active regions in the first direction, and have a bottom with a distance less than the thickness of the isolation layer from the first face; forming word line gate structures within the first recesses; thinning the first substrate from the second face; and forming on the second face bit lines, wherein one active region and one bit line are electrically interconnected.
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