公开(公告)号：US20240292606A1

公开(公告)日：2024-08-29

申请号：US18574057

申请日：2021-09-02

Applicant: ICLEAGUE TECHNOLOGY CO., LTD.

Inventor： Wenyu HUA ,  Fandong LIU ,  Xiao DING

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/038 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor structure and a formation method therefor. The semiconductor structure comprises: a substrate, which has opposite first and second surfaces, and comprises several discrete active areas arranged in a first direction and parallel to a second direction, wherein the first direction is perpendicular to the second direction; word line gate structures, which are disposed in the active areas, extend from the first surface to the second surface, are arranged in the second direction, and run through the active areas along the first direction; a first isolation structure, which is disposed in the substrate and extends from the second surface to the first surface; bit line structures, which are disposed on the first surface, electrically coupled with the active areas, arranged in the first direction, and parallel to the second direction; and capacitor structures, which are disposed on the second surface and electrically coupled with the active areas.

公开(公告)号：US20240188276A1

公开(公告)日：2024-06-06

申请号：US17782791

申请日：2021-08-06

Applicant: ICLEAGUE TECHNOLOGY CO., LTD.

Inventor： Wenyu HUA ,  Fandong LIU ,  Xiao DING

IPC: H10B12/00 ,  G11C11/4091

CPC classification number: H10B12/09 ,  H10B12/315 ,  H10B12/50 ,  G11C11/4091

Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.