公开(公告)号：US20240341089A1

公开(公告)日：2024-10-10

申请号：US18474699

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hosang LEE ,  Taejin PARK ,  Hyunjin LEE ,  Heejae CHAE ,  Yun CHOI

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/482

Abstract: A semiconductor device according to some example embodiments includes: a substrate that includes an active region between element isolation layers; a word line that overlaps the active region and extends in a first direction; a bit line that overlaps the active region and extends in a second direction crossing the first direction; a buried contact connected to the active region; a first pad between and connecting the active region and the bit line; a second pad between and connecting the active region and the buried contact; and a landing pad connected to the buried contact. Each of the element isolation layers includes a first element isolation layer and a second element isolation layer inside the first element isolation layer, and each of the first pad and the second pad are between the element isolation layers.

公开(公告)号：US20240334683A1

公开(公告)日：2024-10-03

申请号：US18613525

申请日：2024-03-22

Applicant: Applied Materials, Inc.

Inventor： Tong Liu ,  Sony Varghese ,  Zhijun Chen ,  Balasubramanian Pranatharthiharan ,  Anand N. Iyer

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer (e.g., tungsten (W)) on a top surface of the insulating dielectric islands and on the bitline metal stack.

公开(公告)号：US20240306378A1

公开(公告)日：2024-09-12

申请号：US18241335

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor device includes a substrate having a cell active region; a word line on the cell active region; a bit line electrically connected to the cell active region; a connection structure in the word line; and a word line contact plug in contact with the connection structure. The word line may include a gate electrode, and the connection structure may be disposed on the gate electrode. The connection structure and the gate electrode may include different materials from each other.

公开(公告)号：US20240284661A1

公开(公告)日：2024-08-22

申请号：US18171662

申请日：2023-02-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Sheng Chieh TSAI

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02 ,  H10B12/485

Abstract: The manufacturing method of a semiconductor device includes providing a word line structure and a hard mask stack on the word line structure. The word line structure includes an active area, a word line, an isolation structure and a protection layer, the word line covers a portion of the active area, the isolation structure is adjacent to the active area and the word line, and the protection layer covers the active area, the word line, and the isolation structure. A first photolithography process is performed to etch the hard mask stack by using a photomask along a first direction. A second photolithography process is performed to etch the hard mask stack by using a photomask along a second direction. A protection pillar covering the portion of the active area by etching the protection layer is formed by using the hard mask stack as a mask.

公开(公告)号：US20240179894A1

公开(公告)日：2024-05-30

申请号：US18499871

申请日：2023-11-01

Applicant: Micron Technology, Inc.

Inventor： Ping Chieh Chiang

IPC: H10B12/00 ,  H01L29/40 ,  H01L29/49

CPC classification number: H10B12/488 ,  H01L29/401 ,  H01L29/49 ,  H10B12/02

Abstract: Methods, apparatuses, and systems related to a metal sense line contact are described. An example apparatus includes a sense line pillar comprising a barrier material over a semiconductor substrate. The sense line pillar further includes a liner material adjacent the barrier material. The sense line pillar further includes a first metal material over the barrier material. The sense line pillar further includes a second metal material over the first metal material. The sense line pillar further includes a cap material over the second metal material. The apparatus further cell contacts between a plurality of sense line pillars.

公开(公告)号：US20240155834A1

公开(公告)日：2024-05-09

申请号：US18536586

申请日：2023-12-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： YI JIANG ,  Qinghua HAN ,  Deyuan XIAO ,  Yunsong QIU

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: The method of forming the semiconductor structure comprises operations of: forming a substrate, and forming active regions located above the substrate and arranged at intervals in a first direction parallel to a top face of the substrate; and performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines each of which extends in the first direction and is electrically connected with a plurality of the active regions arranged at intervals in the first direction

公开(公告)号：US20240147705A1

公开(公告)日：2024-05-02

申请号：US18097236

申请日：2023-01-14

Applicant: SEMES CO,. LTD.

Inventor： Thomas Jongwan KWON ,  Yun Sang KIM ,  Hae Won CHOI

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device including memory cells that are three-dimensionally arranged is provided. The semiconductor device includes: a stack structure including first and second layers, which are sequentially stacked on a substrate, the first layer including first and second semiconductor patterns, which are spaced apart from each other and extend in a first direction, and a first bitline, which extends in a second direction different from the first direction and is electrically connected to the first and second semiconductor patterns, the second layer including third and fourth semiconductor patterns, which are spaced apart from each other and extend in the first direction, and a second bitline, which extends in the second direction and is electrically connected to the third and fourth semiconductor patterns, and each of the first through fourth semiconductor patterns including a source, a channel, a drain, and a bottom electrode; a first wordline connecting the channels of the first and third semiconductor patterns in a vertical direction; a second wordline connecting the channels of the second and fourth semiconductor patterns in the vertical direction.

公开(公告)号：US20240107740A1

公开(公告)日：2024-03-28

申请号：US18531765

申请日：2023-12-07

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Huihui GUI

IPC: H10B12/00 ,  H01L23/00

CPC classification number: H10B12/02 ,  H01L24/08 ,  H01L24/80 ,  H10B12/315 ,  H10B12/482 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1436

Abstract: A method for manufacturing a semiconductor structure includes: forming first base which includes first substrate and active areas arranged in an array along first direction and second direction in first substrate, word lines being disposed in first base, extending along second direction and covering at least opposite sides of each active area; forming charge storage structures electrically connected with first ends of active areas on first base; forming second base which includes second substrate and bit lines disposed in second substrate, bit lines extending along first direction; connecting first base and second base by using a first surface of first base away from charge storage structures and a second surface of second base having structures of bit lines as connection surfaces, bit lines being electrically connected with second ends of active areas, and each first end being disposed opposite to a corresponding second end.

公开(公告)号：US20240090205A1

公开(公告)日：2024-03-14

申请号：US18150934

申请日：2023-01-06

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yongli Zhao ,  Zhicheng Shi ,  Yachao Xu ,  Yong Lu

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/488 ,  H01L29/4236 ,  H10B12/02 ,  H10B12/485

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a word line, and at least two dielectric layers. The word line is arranged in the substrate; the at least two dielectric layers are located between the word line and the substrate and have different dielectric constants.

公开(公告)号：US20240064969A1

公开(公告)日：2024-02-22

申请号：US18153355

申请日：2023-01-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yizhi ZENG

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/02

Abstract: Embodiments provide a semiconductor structure and fabricating method. The method includes: providing a substrate having active structures, where each active structure has a bit line contact region; forming conductive support strips spaced along a first direction, where each conductive support strip extends along a second direction, each conductive support strip connects the bit line contact regions, the bit line contact regions are arranged along the second direction, and the first direction intersects the second direction; forming an initial isolation structure covering a side surface and a top surface of each conductive support strip; removing the initial isolation structure positioned on the top surface of each conductive support strip; removing the conductive support strip by at least a portion of thickness to form a first filling region; where a retained portion of the initial isolation structure forms an isolation structure; and forming a bit line structure in the first filling region.