公开(公告)号：US20230124602A1

公开(公告)日：2023-04-20

申请号：US18079822

申请日：2022-12-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Xin Wang ,  Cheng Gan ,  Wu Tian

IPC: H10B43/40 ,  H10B41/41

Abstract: Disclosed in the application are a semiconductor device structure and a manufacturing method thereof. The semiconductor device structure includes: a semiconductor substrate; active regions and isolation structures located in the semiconductor substrate and arranged alternately at intervals in a first direction, the active regions extending in a second direction perpendicular to the first direction; gate structures located at least on the active regions; and virtual structures located at least on the isolation structures, a spacing existing between the gate structures and the virtual structures in the second direction. The active regions further include source-doped regions and drain-doped regions located on two sides of the gate structures, projections of the virtual structures on the isolation structures are located between the source-doped regions, or projections of the virtual structures on the isolation structures are located between the drain-doped regions.

公开(公告)号：US11437464B2

公开(公告)日：2022-09-06

申请号：US16729818

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Cheng Gan ,  Wei Liu ,  Shunfu Chen

IPC: H01L23/528 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/64 ,  H01L49/02 ,  H01L21/762 ,  H01L23/00

Abstract: Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

公开(公告)号：US11031282B2

公开(公告)日：2021-06-08

申请号：US16730127

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Wei Liu ,  Cheng Gan

IPC: H01L21/762 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

公开(公告)号：US12136449B2

公开(公告)日：2024-11-05

申请号：US17550604

申请日：2021-12-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Cheng Gan ,  Xin Wu ,  Wei Liu

IPC: G11C11/24 ,  G11C11/404 ,  H01L49/02 ,  H10B12/00

Abstract: A capacitor is provided. The capacitor includes a substrate, at least two conductive plates formed in the substrate and extending into the substrate, at least one insulating structure formed between two adjacent conductive plates of the at least two conductive plates and extending into the substrate, and a plurality of contacts, each extending into respective one of the at least two conductive plates.

公开(公告)号：US11264455B2

公开(公告)日：2022-03-01

申请号：US16730225

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wei Liu ,  Shunfu Chen ,  Cheng Gan

IPC: H01L23/48 ,  H01L27/1157 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor device arrays and forming a first interconnect layer on the plurality of semiconductor device arrays. The method also includes forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first and second interconnect layers and forming one or more isolation trenches through a second side of the first substrate that is opposite to the first side to expose a portion of the first side of the first substrate. The one or more isolation trenches are formed between first and second semiconductor device arrays of the plurality of semiconductor devices arrays. The method further includes disposing an isolation material to form one or more isolation structures respectively in the one or more isolation trenches.

公开(公告)号：US20210013088A1

公开(公告)日：2021-01-14

申请号：US16730127

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Wei Liu ,  Cheng Gan

IPC: H01L21/762 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

公开(公告)号：US20240389331A1

公开(公告)日：2024-11-21

申请号：US18792202

申请日：2024-08-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H10B43/40 ,  G11C16/04 ,  G11C16/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41

Abstract: In certain aspects, a semiconductor device includes a substrate and a first transistor. The first transistor includes a first well in the substrate and having a recess, a recess gate structure including a protrusion structure, and a first source and a first drain spaced apart by the recess gate structure. The protrusion structure extends into the recess of the first well. The recess gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric.

公开(公告)号：US20230005946A1

公开(公告)日：2023-01-05

申请号：US17510752

申请日：2021-10-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanwei Shi ,  Yanhong Wang ,  Cheng Gan ,  Liang Chen ,  Wei Liu ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC: H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11529 ,  G11C16/04 ,  G11C16/24 ,  H01L25/00

Abstract: In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

公开(公告)号：US11538780B2

公开(公告)日：2022-12-27

申请号：US16729821

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Wei Liu ,  Cheng Gan

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/762 ,  H01L23/528 ,  H01L25/18 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.

公开(公告)号：US11177343B2

公开(公告)日：2021-11-16

申请号：US16730039

申请日：2019-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Cheng Gan ,  Wei Liu ,  Liang Chen

IPC: H01L21/8238 ,  H01L29/06 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.