公开(公告)号：US20240079057A1

公开(公告)日：2024-03-07

申请号：US17930279

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Paolo Tessariol ,  Umberto Maria Meotto

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US11818893B2

公开(公告)日：2023-11-14

申请号：US17819009

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H01L2223/54426

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US20230118763A1

公开(公告)日：2023-04-20

申请号：US18083420

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

IPC: H10B43/27 ,  H10B41/10 ,  H10B43/35 ,  H10B41/27 ,  H10B43/10 ,  H10B41/35

Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11563024B2

公开(公告)日：2023-01-24

申请号：US17002339

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220223613A1

公开(公告)日：2022-07-14

申请号：US17146193

申请日：2021-01-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US11302634B2

公开(公告)日：2022-04-12

申请号：US16790148

申请日：2020-02-13

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US20220077236A1

公开(公告)日：2022-03-10

申请号：US17497461

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Paolo Tessariol

IPC: H01L27/24 ,  G11C8/08

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

公开(公告)号：US20220068952A1

公开(公告)日：2022-03-03

申请号：US17002339

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220068317A1

公开(公告)日：2022-03-03

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C5/06 ,  H01L21/50 ,  H01L25/065 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11244954B2

公开(公告)日：2022-02-08

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.