知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.016 seconds)

    Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions
    2.
    发明申请
    Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions 有权
    存储阵列，半导体结构和形成半导体结构的方法

    公开(公告)号：US20150014766A1

    公开(公告)日：2015-01-15

    申请号：US14502978

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

    IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

    Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED SYSTEMS AND METHODS
    3.
    发明申请
    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20230010799A1

    公开(公告)日：2023-01-12

    申请号：US17373258

    申请日：2021-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

    IPC: H01L29/417 ,  H01L23/528 ,  H01L21/768 ,  H01L29/40

    Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

    Selective dielectric deposition
    4.
    发明授权
    Selective dielectric deposition 有权

    公开(公告)号：US10937690B2

    公开(公告)日：2021-03-02

    申请号：US16364841

    申请日：2019-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Anish Khandekar ,  Lars P. Heineck ,  Silvia Borsari ,  Zhiqiang Xie

    IPC: H01L21/768 ,  H01L21/311

    Abstract: Methods, apparatuses, and systems related to selectively depositing a liner material on a sidewall of an opening are described. An example method includes forming a liner material on a dielectric material of sidewalls of an opening and a bottom surface of an opening and removing the first liner material of the sidewalls of the opening and the bottom surface of the opening using a non-selective etch chemistry. The example method further includes forming a second liner material on the dielectric material of the sidewalls of the opening to avoid contact with the bottom surface of the opening.

    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    6.
    发明公开
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20240079361A1

    公开(公告)日：2024-03-07

    申请号：US17929997

    申请日：2022-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Lars P. Heineck

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

    Abstract: A microelectronic device includes a memory array region, a control logic region overlying the memory array region, and a pad region overlying the control logic region. The memory array region includes a stack structure including vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically underlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically overlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region includes control logic devices configured to effectuate control operations for the vertically extending strings of memory cells. The pad region includes conductive pad structures coupled to the control logic devices. Memory devices and electronic systems are also described.

    Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
    9.
    发明授权
    Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions 有权
    存储阵列，半导体结构以及形成半导体结构的方法

    公开(公告)号：US09318493B2

    公开(公告)日：2016-04-19

    申请号：US14502978

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

    IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778 ,  H01L21/28 ,  H01L29/78

    CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

    Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

    Circuit Structures, Memory Circuitry, And Methods
    10.
    发明申请
    Circuit Structures, Memory Circuitry, And Methods 有权
    电路结构，存储器电路和方法

    公开(公告)号：US20140273358A1

    公开(公告)日：2014-09-18

    申请号：US14287659

    申请日：2014-05-27

    Applicant: Micron Technology, Inc.

    Inventor： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

    IPC: H01L29/66 ,  H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

    Abstract translation: 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

Patent Agency Ranking