公开(公告)号：US20250071987A1

公开(公告)日：2025-02-27

申请号：US18760750

申请日：2024-07-01

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi

IPC: H10B41/27 ,  H10B41/35

Abstract: A method of forming a microelectronic device includes forming a top dielectric material over a preliminary stack structure, forming a first slot, partially defined by sidewalls, through the top dielectric material, the preliminary stack structure, and a base structure, forming a first mask material over the sidewalls, forming a trim material over the first mask material, removing portions of the trim material, removing portions of at least the first mask material to form a mask material edge, forming a preliminary separator structure at the mask material edge, and forming a vertical memory string structure. The preliminary stack structure includes tiers having a first material and an insulative material. The vertical memory string structure is horizontally adjacent to the preliminary separator structure. Related microelectronic devices, memory devices, and electronic devices are also disclosed.

公开(公告)号：US20250031374A1

公开(公告)日：2025-01-23

申请号：US18745903

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi

IPC: H10B43/27

Abstract: A method of forming a microelectronic device includes forming a preliminary stack structure over a base structure, forming a first slot vertically extending through the preliminary stack structure, forming a dielectric mask material over exposed surfaces of sidewalls of the preliminary stack structure partially defining the first slot, forming gaps in the dielectric mask material, forming voids in sacrificial material and insulative material of the preliminary stack structure via the gaps in the dielectric mask material, forming memory cell material within the voids, and removing a portion of the memory cell material to form vertical memory string structures vertically extending through the preliminary stack structure. Related microelectronic devices, electronic devices, and related methods are also disclosed.

公开(公告)号：US20250008727A1

公开(公告)日：2025-01-02

申请号：US18886735

申请日：2024-09-16

Applicant: Micron Technology, Inc.

Inventor： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

IPC: H10B41/41 ,  B81B7/02 ,  G11C7/10 ,  G11C16/24 ,  H10B41/20 ,  H10B43/20 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240420770A1

公开(公告)日：2024-12-19

申请号：US18813391

申请日：2024-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masanobu Saito

IPC: G11C16/10 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, and a second field-effect transistor between the data line and a second string of series-connected memory cells, wherein a control gate of the first field-effect transistor is connected to a control gate of the second field-effect transistor, and wherein a channel of the first field-effect transistor was fabricated to have a first threshold voltage and a channel of the second field-effect transistor was fabricated to have a second threshold voltage, different than the first threshold voltage.

公开(公告)号：US20230255023A1

公开(公告)日：2023-08-10

申请号：US17665346

申请日：2022-02-04

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Yoshiaki Fukuzumi ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/0483

Abstract: Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.

公开(公告)号：US11386966B2

公开(公告)日：2022-07-12

申请号：US17111770

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.

公开(公告)号：US11227869B1

公开(公告)日：2022-01-18

申请号：US17111746

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  G11C16/34 ,  H01L27/11582

Abstract: Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.

公开(公告)号：US12237259B2

公开(公告)日：2025-02-25

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/35 ,  H10B43/35

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US12100454B2

公开(公告)日：2024-09-24

申请号：US17734623

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Akira Goda

IPC: G11C16/08 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

公开(公告)号：US20240162325A1

公开(公告)日：2024-05-16

申请号：US18421820

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Lindemann ,  Collin Howder ,  Yoshiaki Fukuzumi ,  Richard J. Hill

IPC: H01L29/45 ,  H01L21/28 ,  H01L29/417 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/458 ,  H01L29/40117 ,  H01L29/41725 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.