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    PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY
    1.
    发明申请
    PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY 有权

    公开(公告)号：US20240393977A1

    公开(公告)日：2024-11-28

    申请号：US18636584

    申请日：2024-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Ratna Priyanka Sistla ,  Dan Xu ,  Tomoko Ogura Iwasaki ,  Caixia Yang ,  Lee-eun Yu

    IPC: G06F3/06

    Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

    CELLULAR SIGNAL MESH NETWORK
    2.
    发明公开
    CELLULAR SIGNAL MESH NETWORK 有权

    公开(公告)号：US20240284161A9

    公开(公告)日：2024-08-22

    申请号：US17365119

    申请日：2021-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Kari Crane ,  Deepti Verma ,  Shruthi Kumara Vadivel ,  Tomoko Ogura Iwasaki ,  Sue-Fern Ng

    IPC: H04W8/18 ,  H04B17/318 ,  H04W28/18 ,  H04W52/02

    CPC classification number: H04W8/183 ,  H04B17/318 ,  H04W28/18 ,  H04W52/0229 ,  H04W52/0261

    Abstract: Methods and devices related to a cellular signal mesh network are described. In an example, a method can include determining, via a processing resource of a first computing device, whether a cellular signal of the first computing device is below a threshold cellular signal, transmitting from the first computing device to a second computing device first signaling including data representing a request for operational data of the second computing device in response to determining that the cellular signal of the first computing device is below the threshold cellular signal, receiving from the second computing device second signaling comprising the operational data of the second computing device, and transmitting from the first computing device to the second computing device third signaling including data representing at least one of: a voice call, a video call, or a message in response to receiving the second signaling comprising the operational data.

    SINGLE-LEVEL CELL PROGRAM-VERIFY, LATCH-LIMITED DATA RECOVERY
    6.
    发明公开
    SINGLE-LEVEL CELL PROGRAM-VERIFY, LATCH-LIMITED DATA RECOVERY 审中-公开

    公开(公告)号：US20230352107A1

    公开(公告)日：2023-11-02

    申请号：US18128463

    申请日：2023-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki

    IPC: G11C29/52 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C29/52

    Abstract: Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.

    Sequential SLC read optimization
    7.
    发明授权
    Sequential SLC read optimization 有权

    公开(公告)号：US11776615B2

    公开(公告)日：2023-10-03

    申请号：US17673302

    申请日：2022-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

    IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

    CPC classification number: G11C11/4087 ,  G06F12/0246 ,  G11C11/4074 ,  G11C11/4085 ,  G06F2212/7201

    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

    APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES
    9.
    发明公开
    APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES 审中-公开

    公开(公告)号：US20230274786A1

    公开(公告)日：2023-08-31

    申请号：US17681976

    申请日：2022-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10

    CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/12005 ,  G11C7/1069 ,  G11C7/1096

    Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

    Vertical string driver for memory array
    10.
    发明授权
    Vertical string driver for memory array 有权

    公开(公告)号：US11688463B2

    公开(公告)日：2023-06-27

    申请号：US16948236

    申请日：2020-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip ,  Tomoko Ogura Iwasaki

    IPC: H01L29/04 ,  G11C16/08 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/04

    Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.

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