公开(公告)号：US20240339158A1

公开(公告)日：2024-10-10

申请号：US18625800

申请日：2024-04-03

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki ,  Yeang Meng Hern ,  Lee-eun Yu ,  Albert Fayrushin ,  Fulvio Rori ,  Justin Bates

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

公开(公告)号：US20240393977A1

公开(公告)日：2024-11-28

申请号：US18636584

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Ratna Priyanka Sistla ,  Dan Xu ,  Tomoko Ogura Iwasaki ,  Caixia Yang ,  Lee-eun Yu

IPC: G06F3/06

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

公开(公告)号：US20240295970A1

公开(公告)日：2024-09-05

申请号：US18593779

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki ,  Lee-eun Yu ,  Yeang Meng Hern

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels. The control logic further causes a series of programming pulses to be applied to the selected wordline, wherein respective memory cells of the set of memory cells are programmed to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude, wherein a second programming pulse in the series of programming pulses has a second magnitude, and wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse increased by a predefined pulse step amount.