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    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
    2.
    发明申请
    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE 有权

    公开(公告)号：US20250004645A1

    公开(公告)日：2025-01-02

    申请号：US18886901

    申请日：2024-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

    IPC: G06F3/06 ,  G11C16/34 ,  G11C29/52

    Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

    Two-tier defect scan management
    3.
    发明授权
    Two-tier defect scan management 有权

    公开(公告)号：US12105967B2

    公开(公告)日：2024-10-01

    申请号：US17894794

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

    Memory devices for multiple read operations
    5.
    发明授权
    Memory devices for multiple read operations 有权

    公开(公告)号：US11756594B2

    公开(公告)日：2023-09-12

    申请号：US17463789

    申请日：2021-09-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/14

    CPC classification number: G11C7/106 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/14 ,  G11C7/222

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    PROGRAM COMMAND GENERATION WITH DUMMY DATA GENERATION AT A MEMORY DEVICE
    6.
    发明申请
    PROGRAM COMMAND GENERATION WITH DUMMY DATA GENERATION AT A MEMORY DEVICE 有权

    公开(公告)号：US20230137866A1

    公开(公告)日：2023-05-04

    申请号：US17974799

    申请日：2022-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Jeremy Binfet ,  Violante Moschiano ,  James Fitzpatrick ,  Kishore Kumar Muccherla ,  Jeffrey S. McNeil ,  Phong Sy Nguyen

    IPC: G06F3/06

    Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

    REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS
    7.
    发明申请
    REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS 有权

    公开(公告)号：US20210398599A1

    公开(公告)日：2021-12-23

    申请号：US16907594

    申请日：2020-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Jason Lee Nevill ,  Tommaso Vali

    IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G06F3/06

    Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.

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