公开(公告)号：US08687430B2

公开(公告)日：2014-04-01

申请号：US13919350

申请日：2013-06-17

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Frankie F. Roohparvar

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3481 ,  G11C27/02 ,  G11C27/024 ,  G11C2211/5634

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

Abstract translation: 公开了存储器件，方法和采样和保持电路，包括包括耦合到位线的采样和保持电路的存储器件。 一个这样的采样和保持电路包括读取电路，验证电路和参考电路。 读取电路存储从所选存储单元读取的读取阈值电压。 验证电路存储与读取的阈值电压相比较的目标阈值电压，以在目标和读取阈值电压基本相等时产生禁止信号。 参考电路存储参考阈值电压，该参考阈值电压可用于转换读取阈值电压以补偿晶体管电压降和/或温度变化。

公开(公告)号：US20130201759A1

公开(公告)日：2013-08-08

申请号：US13796602

申请日：2013-03-12

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3418

Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

Abstract translation: 适于接收和发送表示两个或多个位的位模式的模拟数据信号的存储器件有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。 这种存储器件的编程包括：用粗略的编程脉冲对单元进行初始编程，使其阈值电压以接近编程状态的大步进移动。 然后使用粗略编程对相邻单元进行编程。 然后，该算法返回到初始编程的单元，然后使用一个或多个精细脉冲编程，该精细脉冲以较小步长将阈值电压缓慢移动到最终编程状态阈值电压。

公开(公告)号：US20250029641A1

公开(公告)日：2025-01-23

申请号：US18910412

申请日：2024-10-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. MCNeil ,  Jung-Sheng Hoei

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

公开(公告)号：US08693246B2

公开(公告)日：2014-04-08

申请号：US13749850

申请日：2013-01-25

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/04 ,  G11C16/20 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004

Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.

Abstract translation: 通过向所选择的单元写入电压来执行存储器控制器的自校准。 对所选单元格周围的相邻单元进行编程。 在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。 这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。 通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。 这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。

公开(公告)号：US20230386533A1

公开(公告)日：2023-11-30

申请号：US18232949

申请日：2023-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/106 ,  G11C7/1057 ,  G11C7/222 ,  G11C7/1087 ,  G11C7/14 ,  G11C7/1084

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

公开(公告)号：US09471425B2

公开(公告)日：2016-10-18

申请号：US14308040

申请日：2014-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G06F12/02 ,  G06F11/10 ,  G11C11/56 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

Abstract translation: 用于管理存储在存储设备中的数据的方法便于管理不同密度的存储器的利用。 所述方法包括从具有第一密度的第一页数或块的存储单元读取第一数据，对读取的第一数据执行数据处理操作以产生第二数据，以及将第二数据写入第二数量的页或块 的具有第二密度的存储单元，其中所述第二密度不同于所述第一密度，并且其中所述第二数量不同于所述第一密度。

公开(公告)号：US20130272070A1

公开(公告)日：2013-10-17

申请号：US13919350

申请日：2013-06-17

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Frankie F. Rooparvar

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3481 ,  G11C27/02 ,  G11C27/024 ,  G11C2211/5634

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

公开(公告)号：US08553458B2

公开(公告)日：2013-10-08

申请号：US13721808

申请日：2012-12-20

Applicant: Micron Technology, Inc.

Inventor： Jung-Sheng Hoei

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621

Abstract: Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, wherein each ramped voltage signal segment has a different start voltage and a different end voltage than the other ramped voltage signal segments.

Abstract translation: 公开了用于分段编程，程序验证和存储器件的方法。 用于编程的一种这样的方法包括利用编程电压来偏置存储器单元并且利用多个斜坡电压信号段来对存储器单元进行程序验证，其中每个斜坡电压信号段具有与其它斜坡电压信号不同的起始电压和不同的结束电压 细分。

公开(公告)号：US20130166815A1

公开(公告)日：2013-06-27

申请号：US13770059

申请日：2013-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G06F12/02

CPC classification number: G11C11/5642 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.

Abstract translation: 存储器控制器具有数字信号处理器。 数字信号处理器被配置为输出用于对存储器件的存储器单元进行编程的程序数据的M + N位的数字数据信号。 数字信号处理器被配置为接收从存储器件的存储器单元读取的M + L位的数字数据信号，并从接收的数字数据信号M中取回存储在存储单元中的数据位。

公开(公告)号：US11756594B2

公开(公告)日：2023-09-12

申请号：US17463789

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/106 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/14 ,  G11C7/222

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.