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公开(公告)号：US20240386974A1
公开(公告)日：2024-11-21
申请号：US18662945
申请日：2024-05-13
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Huai-Yuan Tseng , Zhenming Zhou
Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including writing data to an MU of the memory device and performing one or more scan operations on the MU to determine an aggregate value of a data state metric reflective of an amount of erroneous memory cells in the MU. The operations can include determining whether a value of the data state metric reflective of a specified set of erroneous memory cells in the MU satisfies a criterion and identifying a target programming level to which at least one erroneous memory cell was originally programmed. They can also include reprogramming the at least one erroneous memory cell to the target programming level.
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公开(公告)号：US12131060B2
公开(公告)日：2024-10-29
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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公开(公告)号：US20240152279A1
公开(公告)日：2024-05-09
申请号：US17982750
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Pitamber Shukla , Akira Goda
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: An apparatus can include a touch-up component. The touch-up component can detect a first charge parameter for a portion of memory of a memory system. The touch-up component can, subsequent to detecting the first charge parameter a particular time interval, detect a second charge parameter for the portion of memory. The touch-up component can determine a charge parameter change per time interval based on the first charge parameter, the second charge parameter, and the particular time interval. The touch-up component can perform a touch-up operation on the portion of memory at a particular time point based on the charge parameter change per time interval.
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4.发明公开公开(公告)号：US20240054048A1
公开(公告)日：2024-02-15
申请号：US17884432
申请日：2022-08-09
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Mustafa N. Kaynak , Akira Goda , Sivagnanam Parthasarathy , Jonathan Scott Parry
CPC classification number: G06F11/1068 , G06F11/0793 , G06F11/0772
Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.
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公开(公告)号：US20250013529A1
公开(公告)日：2025-01-09
申请号：US18747234
申请日：2024-06-18
Applicant: Micron Technology, Inc.
Inventor： Dung Viet Nguyen , James Fitzpatrick , Huai-Yuan Tseng
IPC: G06F11/10
Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including storing a set of user data and multiple portions of error correction data. The operations can also include, responsive to an expiration of a first threshold amount of time after storing the set of user data, performing, using the third portion of the error correction data, a first error correction operation, on each of the set of user data, the first portion, and the second portion, and rewriting, on the memory device, the set of user data, the first portion, and the second portion. The operations can further include deleting the third portion.
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Patent Agency Ranking
公开(公告)号：US20250013382A1
公开(公告)日：2025-01-09
申请号：US18895273
申请日：2024-09-24
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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公开(公告)号：US20240371452A1
公开(公告)日：2024-11-07
申请号：US18648110
申请日：2024-04-26
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla, , Robert Winston Mason , Huai-Yuan Tseng , Akira Goda , Kishore Kumar Muchherla
Abstract: Methods, systems, and devices for techniques for managing a voltage recovery operation are described. In some cases, as part of performing a write command to store data to a set of memory cells, the memory system may store an indication of the initial time at which the write operation occurred, the temperature of the set of memory cells at the initial time, or both. The memory system may subsequently manage an accumulated value based on a duration from the initial time and the temperature of the set of memory cells during the duration. If the accumulated value exceeds an accumulation threshold, the memory system may identify an indication of degradation of the set of memory cells. If the indication exceeds a degradation threshold, the memory system may perform a voltage recovery operation to modify voltages of the set of memory cells.
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公开(公告)号：US20240185926A1
公开(公告)日：2024-06-06
申请号：US18517903
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Kishore Kumar Mucherla , William Charles Filipiak , Eric N. Lee , Andrew Bicksler , Ugo Russo , Niccolo' Righetti , Christian Caillat , Akira Goda , Ting Luo , Antonino Pollio
CPC classification number: G11C16/102 , G11C16/16 , G11C16/3404
Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.
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公开(公告)号：US20240087651A1
公开(公告)日：2024-03-14
申请号：US17941831
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Akira Goda , Dung V. Nguyen , Giovanni Maria Paolucci , James Fitzpatrick , Eric N. Lee , Dave Scott Ebsen , Tomoharu Tanaka
CPC classification number: G11C16/102 , G11C16/26 , G11C16/32
Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
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公开(公告)号：US20240028252A1
公开(公告)日：2024-01-25
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/064 , G06F3/0604 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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