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    Encoding and decoding data bits stored in a combination of multiple memory cells
    3.
    发明授权
    Encoding and decoding data bits stored in a combination of multiple memory cells 有权

    公开(公告)号：US11550510B2

    公开(公告)日：2023-01-10

    申请号：US17315738

    申请日：2021-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Tomoharu Tanaka

    IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26

    Abstract: A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; translate a combination of the first integer value and the second integer value to a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state and a third set of logical bits corresponding to the second Vt state.

    Multi-deck memory device including buffer circuitry under array
    4.
    发明授权
    Multi-deck memory device including buffer circuitry under array 有权

    公开(公告)号：US11450381B2

    公开(公告)日：2022-09-20

    申请号：US16546720

    申请日：2019-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Tomoharu Tanaka

    IPC: G11C5/02 ,  G11C11/4096 ,  G11C16/16 ,  G06F13/16 ,  G11C11/4094

    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

    MULTI-DECK MEMORY DEVICE INCLUDING BUFFER CIRCUITRY UNDER ARRAY
    5.
    发明申请
    MULTI-DECK MEMORY DEVICE INCLUDING BUFFER CIRCUITRY UNDER ARRAY 有权

    公开(公告)号：US20210057020A1

    公开(公告)日：2021-02-25

    申请号：US16546720

    申请日：2019-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Tomoharu Tanaka

    IPC: G11C11/4096 ,  G11C16/16 ,  G11C11/4094 ,  G11C5/02 ,  G06F13/16

    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

    Current monitoring in semiconductor packages
    6.
    发明授权
    Current monitoring in semiconductor packages 有权

    公开(公告)号：US10803962B1

    公开(公告)日：2020-10-13

    申请号：US16371221

    申请日：2019-04-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tomoharu Tanaka

    IPC: G11C16/30 ,  G11C5/14 ,  G11C16/04 ,  G01R19/10 ,  G06F1/3296 ,  G01R19/165 ,  G06F1/28

    Abstract: A semiconductor package includes an external power supply node, a current monitoring node, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies includes a first circuit and a second circuit. The first circuit is configured to supply a first operating current to that semiconductor die from the external power supply node. The second circuit is configured to mirror the first operating current on a reduced scale and output the mirrored first operating current to the current monitoring node. The mirrored first operating current from each semiconductor die of the plurality of semiconductor dies is summed on the current monitoring node.

    PARTIAL PAGE MEMORY OPERATIONS
    7.
    发明申请
    PARTIAL PAGE MEMORY OPERATIONS 有权
    部分页面记忆操作

    公开(公告)号：US20160232979A1

    公开(公告)日：2016-08-11

    申请号：US15131719

    申请日：2016-04-18

    Applicant: Micron Technology, Inc.

    Inventor： Michael Abraham ,  Tomoharu Tanaka ,  Koichi Kawai ,  Yuichi Einaga

    IPC: G11C16/10 ,  G06F12/02 ,  G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/107 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14

    Abstract: Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

    Abstract translation: 装置可以包括具有以多个层形成的存储器单元串的存储器块。 该装置还可以包括由串共享的访问线和数据线，其中接入线耦合到对应于多个层的相应层的存储单元。 对应于相应层的至少一部分的存储单元可以包括多页的相应页面。 数据线的子集可以被映射到相应页的多个部分页的相应局部页中。 每个部分页面可以独立地从其他部分页面中选择。 公开了附加的装置和方法。

    3D NAND flash memory devices and related electronic systems
    10.
    发明授权
    3D NAND flash memory devices and related electronic systems 有权

    公开(公告)号：US11908512B2

    公开(公告)日：2024-02-20

    申请号：US18148684

    申请日：2022-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Tomoharu Tanaka ,  Yoshiaki Fukuzumi

    IPC: G11C11/4097 ,  G11C11/4091 ,  B81B7/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

    CPC classification number: G11C11/4097 ,  B81B7/008 ,  G11C11/4091 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  B81B2201/07

    Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

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