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公开(公告)号：US12190957B2
公开(公告)日：2025-01-07
申请号：US17939273
申请日：2022-09-07
Applicant: Micron Technology, Inc.
Inventor： Carmine Miccoli , Andrew Bicksler
Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.
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公开(公告)号：US11917825B2
公开(公告)日：2024-02-27
申请号：US17661713
申请日：2022-05-02
Applicant: Micron Technology, Inc.
Inventor： Andrew Bicksler , Wei Yeeng Ng , James C. Brighten
IPC: H10B43/27 , H01L21/768 , H01L23/528 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35
CPC classification number: H10B43/27 , H01L21/76805 , H01L21/76895 , H01L23/5283 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.
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公开(公告)号：US11355514B2
公开(公告)日：2022-06-07
申请号：US16541944
申请日：2019-08-15
Applicant: Micron Technology, Inc.
Inventor： Andrew Bicksler , Wei Yeeng Ng , James C. Brighten
IPC: H01L27/11582 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L21/768 , H01L23/528 , H01L27/1157
Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.
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公开(公告)号：US10126967B2
公开(公告)日：2018-11-13
申请号：US15342287
申请日：2016-11-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC: G06F3/06 , G11C16/04 , G11C16/24 , G11C16/26 , G06F12/0804 , G06F13/28 , G06F12/0846
Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
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公开(公告)号：US09490025B2
公开(公告)日：2016-11-08
申请号：US14143763
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
Abstract translation: 编程存储器件的方法包括将多条数据线的每条数据线偏置到编程禁止电压; 放电多条数据线的数据线的第一部分，其中多条数据线的数据线的第一部分耦合到选择用于编程的存储器单元; 以及将多个编程脉冲施加到被选择用于编程的存储器单元，同时将所述多条数据线的数据线的剩余部分偏置到所述编程禁止电压。
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Patent Agency Ranking
公开(公告)号：US20150029788A9
公开(公告)日：2015-01-29
申请号：US14143763
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
IPC: G11C16/34
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
Abstract translation: 编程存储器件的方法包括将多条数据线的每条数据线偏置到编程禁止电压; 放电多条数据线的数据线的第一部分，其中多条数据线的数据线的第一部分耦合到选择用于编程的存储器单元; 以及将多个编程脉冲施加到被选择用于编程的存储器单元，同时将所述多条数据线的数据线的剩余部分偏置到所述编程禁止电压。
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公开(公告)号：US20240185926A1
公开(公告)日：2024-06-06
申请号：US18517903
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Kishore Kumar Mucherla , William Charles Filipiak , Eric N. Lee , Andrew Bicksler , Ugo Russo , Niccolo' Righetti , Christian Caillat , Akira Goda , Ting Luo , Antonino Pollio
CPC classification number: G11C16/102 , G11C16/16 , G11C16/3404
Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.
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公开(公告)号：US20230065743A1
公开(公告)日：2023-03-02
申请号：US17458954
申请日：2021-08-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrew Bicksler , Marc Aoulaiche
IPC: G11C16/04 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , G11C16/16
Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.
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公开(公告)号：US20210202501A1
公开(公告)日：2021-07-01
申请号：US16735098
申请日：2020-01-06
Applicant: Micron Technology, Inc.
Inventor： Andrew Bicksler , Marc Aoulaiche , Albert Fayrushin
IPC: H01L27/1157 , H01L27/11582 , G11C16/04 , G11C16/24 , G11C16/08 , G11C16/34 , G06F3/06
Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.
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公开(公告)号：US11029861B2
公开(公告)日：2021-06-08
申请号：US16543743
申请日：2019-08-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC: G06F3/06 , G11C16/24 , G11C16/26 , G11C16/04 , G06F12/0804 , G06F13/28 , G06F12/0846
Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.
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