公开(公告)号：US20240427500A1

公开(公告)日：2024-12-26

申请号：US18733350

申请日：2024-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicola Ciocchini ,  Thomas Lentz ,  Ugo Russo

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a set of memory cells of the memory device; identifying a wordline group coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the set of memory cells; determining a current temperature associated with the set of memory cells; determining, based on the threshold voltage offset bin and the current temperature, a read mask identifier associated with the set of memory cells; determining, based on the read mask identifier and the wordline group, a set of threshold voltage offsets associated with the set of memory cells; and performing the read operation using the set of threshold voltage offsets.

公开(公告)号：US20240185897A1

公开(公告)日：2024-06-06

申请号：US18438709

申请日：2024-02-12

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C19/32 ,  H10B41/35 ,  H10B43/27

CPC classification number: G11C7/1006 ,  G11C7/1096 ,  G11C8/12 ,  G11C16/08 ,  G11C19/32 ,  H10B41/35 ,  H10B43/27 ,  G11C11/5621

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

公开(公告)号：US11977774B2

公开(公告)日：2024-05-07

申请号：US17579230

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Ugo Russo ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An average number of program erase cycles (PECs) for a memory device is identified. A set of trims associated with the average number of PECs is identified. One or more write trims associated with the memory device are set according to the set of trims. A write command directed to the memory device is received. The write command is executed according to the one or more write trims.

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US11462281B1

公开(公告)日：2022-10-04

申请号：US17307443

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Eric N. Lee ,  Tong Liu ,  Sheyang Ning ,  Cobie B. Loper ,  Ugo Russo

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

Abstract: Control logic in a memory device identifies a first group of wordlines associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of programming pulses and a first set of program verify operations is executed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the executing of the first dynamic start voltage operation includes causing the first set of programming pulses to be applied to at least a portion of the first group of wordlines. A second set of programming pulses including at least one programming pulse having the first dynamic start voltage level are caused to be applied to the first group of wordlines to program a second portion of the first subset of memory cells of the set of memory cells. A second group of wordlines associated with a second subset of memory cells to be programmed is identified. A second dynamic start voltage operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second dynamic start voltage level.

公开(公告)号：US11211399B2

公开(公告)日：2021-12-28

申请号：US16542061

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Chris M. Carlson

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  G11C5/06

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US20210050363A1

公开(公告)日：2021-02-18

申请号：US16542061

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Chris M. Carlson

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/1157

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US10658428B2

公开(公告)日：2020-05-19

申请号：US16185729

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L45/00

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

公开(公告)号：US09449683B2

公开(公告)日：2016-09-20

申请号：US14596293

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Fabio Pellizzer

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  G11C11/56

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/16

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

公开(公告)号：US20150340408A1

公开(公告)日：2015-11-26

申请号：US14285286

申请日：2014-05-22

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between the memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

Abstract translation: 相变存储装置包括存储单元，其包括相变材料，电耦合到至少一些存储单元的对准组的位线以及电耦合到存储单元的相变材料的加热元件。 加热元件包括沿位线方向延伸的垂直部分。 附加的相变存储装置包括位于存储器列和基极接触柱之间的虚拟列。 虚拟列包括相变存储单元，并且没有耦合到其相变存储单元的加热元件。 附加的相变存储装置包括可操作地耦合到相变存储器单元的加热元件。 加热元件和相变存储器单元之间的界面面积具有与位线宽度无关的长度。 方法涉及形成这种相变存储装置。