公开(公告)号：US09111631B2

公开(公告)日：2015-08-18

申请号：US14325183

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Mattia Robustelli ,  Silvia Beltrami ,  Laura Tatiana Czeppel ,  Massimo Ernesto Bertuccio

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入存储器件的性能。

公开(公告)号：US20230214133A1

公开(公告)日：2023-07-06

申请号：US18090449

申请日：2022-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Jeffrey S. McNeil ,  Niccolo' Righetti ,  Silvia Beltrami ,  Violante Moschiano ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

公开(公告)号：US20210027842A1

公开(公告)日：2021-01-28

申请号：US17068000

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.

公开(公告)号：US10586597B2

公开(公告)日：2020-03-10

申请号：US16019631

申请日：2018-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

公开(公告)号：US20140293698A1

公开(公告)日：2014-10-02

申请号：US14301798

申请日：2014-06-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/34

CPC classification number: G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3468 ,  G11C16/3486 ,  G11C16/3495

Abstract: Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.

Abstract translation: 本公开的某些方面涉及使用具有具有电平的新编程电压的至少一个编程脉冲来编程至少一个闪存单元。 该电平被维持在闪速存储器控制器存储器的块中的至少一个页面中，其中该电平根据应用于至少一个闪存单元的编程周期的数量而变化。

公开(公告)号：US12131028B2

公开(公告)日：2024-10-29

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US20190355423A1

公开(公告)日：2019-11-21

申请号：US16525804

申请日：2019-07-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/12

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

公开(公告)号：US20140321206A1

公开(公告)日：2014-10-30

申请号：US14325183

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Mattia Robustelli ,  Silvia Beltrami ,  Laura Tatiana Czeppel ,  Massimo Ernesto Bertuccio

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入存储器件的性能。

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US11430522B2

公开(公告)日：2022-08-30

申请号：US17068000

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.