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    Memory cell biasing techniques during a read operation
    1.
    发明授权
    Memory cell biasing techniques during a read operation 有权

    公开(公告)号：US12237002B2

    公开(公告)日：2025-02-25

    申请号：US17741136

    申请日：2022-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

    IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097

    Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

    Data masking for memory
    2.
    发明授权
    Data masking for memory 有权

    公开(公告)号：US12050784B2

    公开(公告)日：2024-07-30

    申请号：US17730777

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Jahanshir Javanifard ,  Daniele Vimercati

    IPC: G06F3/06

    CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

    Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

    Managing memory based on access duration
    3.
    发明授权
    Managing memory based on access duration 有权

    公开(公告)号：US12002505B2

    公开(公告)日：2024-06-04

    申请号：US17649104

    申请日：2022-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Pazzocco ,  Angelo Visconti

    IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

    CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093

    Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

    DIFFERENTIAL STORAGE IN MEMORY ARRAYS
    4.
    发明公开
    DIFFERENTIAL STORAGE IN MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240127877A1

    公开(公告)日：2024-04-18

    申请号：US18047568

    申请日：2022-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Durai Vishak Nirmal Ramaswamy ,  Giorgio Servalli ,  Angelo Visconti ,  Marcello Mariani ,  Alessandro Calderoni

    IPC: G11C11/22 ,  G11C7/06

    CPC classification number: G11C11/2257 ,  G11C7/067 ,  G11C11/2297

    Abstract: Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

    Erasure decoding for a memory device
    5.
    发明授权
    Erasure decoding for a memory device 有权

    公开(公告)号：US11301320B2

    公开(公告)日：2022-04-12

    申请号：US16840286

    申请日：2020-04-03

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal ,  Angelo Visconti

    IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G11C11/22 ,  G11C11/4091

    Abstract: Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

    CHARGE LEAKAGE DETECTION FOR MEMORY SYSTEM RELIABILITY
    6.
    发明申请
    CHARGE LEAKAGE DETECTION FOR MEMORY SYSTEM RELIABILITY 有权

    公开(公告)号：US20210304805A1

    公开(公告)日：2021-09-30

    申请号：US16831524

    申请日：2020-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Riccardo Pazzocco ,  Jonathan J. Strand ,  Kevin T. Majerus

    IPC: G11C11/22 ,  G11C29/50

    Abstract: Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

    OPEN PAGE BIASING TECHNIQUES
    7.
    发明申请
    OPEN PAGE BIASING TECHNIQUES 有权

    公开(公告)号：US20210193210A1

    公开(公告)日：2021-06-24

    申请号：US17143800

    申请日：2021-01-07

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

    Memory management for charge leakage in a memory device
    8.
    发明授权
    Memory management for charge leakage in a memory device 有权

    公开(公告)号：US10984847B2

    公开(公告)日：2021-04-20

    申请号：US16441722

    申请日：2019-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti

    IPC: G11C11/22 ,  G11C11/4091

    Abstract: Methods, systems, and devices for memory management associated with charge leakage in a memory device are described. A memory device may identify a charge leakage associated with one or more memory cells or access lines, and may determine whether to invert a logic state stored by a memory cell or a set of memory cells to improve the likelihood that the memory cells are read properly in the presence of charge leakage. In some examples, the memory device may also store an indication that the complement of the detected logic state was written, such as a bit flip indication, which may correspond to one memory cell or a set of memory cells.

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