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    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    1.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 审中-公开

    公开(公告)号：US20230298652A1

    公开(公告)日：2023-09-21

    申请号：US18200871

    申请日：2023-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    CPC classification number: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    Memory systems and memory programming methods
    2.
    发明授权
    Memory systems and memory programming methods 有权

    公开(公告)号：US11024378B2

    公开(公告)日：2021-06-01

    申请号：US16176417

    申请日：2018-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Emiliano Faraoni ,  Scott E. Sills ,  Alessandro Calderoni ,  Adam Johnson

    IPC: G11C13/00

    Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

    Cell performance recovery using cycling techniques
    6.
    发明授权
    Cell performance recovery using cycling techniques 有权

    公开(公告)号：US09786349B1

    公开(公告)日：2017-10-10

    申请号：US15201220

    申请日：2016-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/22

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/2293

    Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

    Memory systems and memory programming methods
    7.
    发明授权
    Memory systems and memory programming methods 有权
    内存系统和内存编程方法

    公开(公告)号：US09269432B2

    公开(公告)日：2016-02-23

    申请号：US14151729

    申请日：2014-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Emiliano Faraoni ,  Scott E. Sills ,  Alessandro Calderoni ,  Adam Johnson

    IPC: G11C13/00

    CPC classification number: G11C13/0064 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

    Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

    Abstract translation: 描述了存储器系统和存储器编程方法。 根据一种布置，存储器系统包括存储器阵列，该存储器阵列包括单独配置成具有多个不同存储器状态的多个存储器单元，其被配置为将信号施加到存储器单元以将存储器单元编程到不同的存储器状态， 以及控制器，被配置为控制所述访问电路以将所述信号中的第一信号施加到所述存储器单元之一，以将所述一个存储器单元从第一存储器状态编程到与所述第一存储器状态不同的第二存储器状态，以确定所述 作为施加第一信号的结果，一个存储器单元不能进入第二存储器状态，并且控制访问电路将第二信号施加到一个存储器单元，以将一个存储器单元从第一存储器状态编程为 作为确定结果的第二存储器状态，其中第一和第二信号具有不同的电特性。

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    9.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    MEMORY CELL IMPRINT AVOIDANCE
    10.
    发明申请
    MEMORY CELL IMPRINT AVOIDANCE 有权

    公开(公告)号：US20210280231A1

    公开(公告)日：2021-09-09

    申请号：US17211246

    申请日：2021-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

    IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

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