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    APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD
    3.
    发明申请
    APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD 有权

    公开(公告)号：US20170098660A1

    公开(公告)日：2017-04-06

    申请号：US15379933

    申请日：2016-12-15

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Adam D. Johnson

    IPC: H01L27/11597 ,  G11C11/22

    CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

    Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

    Switching Components and Memory Units
    4.
    发明申请
    Switching Components and Memory Units 有权
    切换组件和内存单元

    公开(公告)号：US20150236259A1

    公开(公告)日：2015-08-20

    申请号：US14184400

    申请日：2014-02-19

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2409 ,  G11C11/16 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

    Abstract: Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior.

    Abstract translation: 一些实施例包括开关组件，其包括一对电极之间的选择器区域。 选择器区域包含掺杂有氮，氧，锗和碳中的一种或多种的硅。 一些实施例包括存储器单元，其包括电存储器单元电存储单元和选择器件。 选择装置在一对电极之间具有选择器区域。 选择器区域包含掺杂有氮，氧，锗和碳中的一种或多种的半导体。 选择器件具有电流对电压特性，其包括回跳电压特性。

    THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE
    5.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE 有权
    三维存储器与选择器件阵列

    公开(公告)号：US20140361239A1

    公开(公告)日：2014-12-11

    申请号：US13915302

    申请日：2013-06-11

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Scott E. Sills ,  Gurtej S. Sandhu

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/11578 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

    Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

    Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部， 至少一个导电延伸部与多个第一导电线中的每一个相交。 存储元件材料布置在至少一个导电延伸部周围，并且选择装置围绕存储元件材料布置。 存储元件材料与分离多个第一导电线的绝缘材料径向相邻，并且围绕存储元件材料布置的多个材料径向地邻近多个第一导电线中的每一个。

    Charge-Retaining Transistor, Array Of Memory Cells, and Methods Of Forming A Charge-Retaining Transistor
    6.
    发明申请
    Charge-Retaining Transistor, Array Of Memory Cells, and Methods Of Forming A Charge-Retaining Transistor 有权
    电荷保持晶体管，存储单元阵列和形成电荷保持晶体管的方法

    公开(公告)号：US20140339624A1

    公开(公告)日：2014-11-20

    申请号：US13894481

    申请日：2013-05-15

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy

    IPC: H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/28556 ,  H01L21/28568 ,  H01L27/11556 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

    Abstract: A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.

    Abstract translation: 电荷保持晶体管包括控制栅极和控制栅极旁边的栅极间电介质。 晶体管的电荷存储节点包括沿着栅极间电介质的第一半导体材料。 电荷捕获材料岛与第一种半导体材料相邻。 氧化保护材料与岛屿一起。 第二半导体材料与氧化保护材料一起，并且与氧化保护材料的组成不同。 隧道电介质与电荷存储节点一起。 通道材料与隧道电介质一起。 公开了包括方法的其它实施例。

    Memory Programming Methods And Memory Systems
    7.
    发明申请
    Memory Programming Methods And Memory Systems 有权
    内存编程方法和内存系统

    公开(公告)号：US20140112052A1

    公开(公告)日：2014-04-24

    申请号：US13658519

    申请日：2012-10-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jonathan Strand ,  Adam Johnson ,  Xiaonan Chen ,  D.V. Nirmal Ramaswamy

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0064 ,  G11C29/08 ,  G11C29/50008 ,  G11C2013/0073 ,  G11C2029/0409 ,  G11C2029/5006

    Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

    Abstract translation: 描述了存储器编程方法和存储器系统。 一个示例性存储器编程方法包括：首先将第一信号施加到存储器单元以尝试将存储器单元编程到期望状态，其中第一信号对应于期望状态，在第一次施加之后，确定存储器单元不能放置 在所需状态下，在确定之后，向存储单元施加第二信号，其中第二信号对应于与期望状态不同的另一状态，并且在第二次施加之后，第三信号施加到存储单元 将存储器单元编程到所需状态，其中第三信号对应于期望状态。 描述附加的方法和装置。

    Memory Cells and Methods of Storing Information
    8.
    发明申请
    Memory Cells and Methods of Storing Information 有权

    公开(公告)号：US20130299893A1

    公开(公告)日：2013-11-14

    申请号：US13944235

    申请日：2013-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej S. Sandhu ,  D.V. Nirmal Ramaswamy

    IPC: H01L29/792

    CPC classification number: H01L29/792 ,  G11C16/0416 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/788

    Abstract: Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell.

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