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公开(公告)号：US20240331754A1
公开(公告)日：2024-10-03
申请号：US18742089
申请日：2024-06-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Chao-I Wu , Sheng-Chen Wang , Yu-Ming Lin
CPC classification number: G11C11/2257 , G11C11/223 , G11C11/2255 , H10B43/27 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
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公开(公告)号：US12089416B2
公开(公告)日：2024-09-10
申请号：US18332972
申请日：2023-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Yunseong Lee , Sanghyun Jo
CPC classification number: H10B51/30 , G11C11/223 , H01L29/40111 , H01L29/6684 , H01L29/78391 , G06N3/065
Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
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公开(公告)号：US12051750B2
公开(公告)日：2024-07-30
申请号：US17884285
申请日：2022-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC: H01L29/78 , G11C11/22 , H01L29/04 , H01L29/24 , H01L29/66 , H01L29/786 , H10B51/10 , H10B51/20 , H10B51/30
CPC classification number: H01L29/78391 , G11C11/223 , G11C11/2255 , G11C11/2257 , H01L29/04 , H01L29/24 , H01L29/66969 , H01L29/7869 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.
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公开(公告)号：US20240242750A1
公开(公告)日：2024-07-18
申请号：US18420171
申请日：2024-01-23
Inventor： Shih-Lien Linus Lu
CPC classification number: G11C11/2255 , G11C11/223 , G11C11/2257 , H01L29/78391 , H10B51/30
Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.
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公开(公告)号：US12040006B2
公开(公告)日：2024-07-16
申请号：US17815032
申请日：2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Chao-I Wu , Sheng-Chen Wang , Yu-Ming Lin
CPC classification number: G11C11/2257 , G11C11/223 , G11C11/2255 , H10B43/27 , H10B51/10 , H10B51/20 , H10B51/30
Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
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公开(公告)号：US20240233795A1
公开(公告)日：2024-07-11
申请号：US18615398
申请日：2024-03-25
Inventor： Huan-Sheng WEI , Tzer-Min SHEN , Zhiqiang WU
CPC classification number: G11C11/2275 , G11C11/223 , G11C11/2273 , H10B51/30 , H10B51/40
Abstract: A memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (IGZO), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. The memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.
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公开(公告)号：US12002499B2
公开(公告)日：2024-06-04
申请号：US17868982
申请日：2022-07-20
Inventor： Sheng-chen Wang , Meng-Han Lin , Chia-En Huang , Yi-Ching Liu
IPC: G11C11/22 , H01L23/528 , H10B51/20 , H10B51/30
CPC classification number: G11C11/2259 , G11C11/223 , H01L23/528 , H10B51/20 , H10B51/30
Abstract: Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.
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8.发明公开
公开(公告)号：US20240114691A1
公开(公告)日：2024-04-04
申请号：US18525301
申请日：2023-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Sheng Chang
CPC classification number: H10B51/30 , G11C11/223 , G11C11/2275 , G11C11/2297 , H01L28/75
Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.
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公开(公告)号：US11942134B2
公开(公告)日：2024-03-26
申请号：US18056807
申请日：2022-11-18
Inventor： Huan-Sheng Wei , Tzer-Min Shen , Zhiqiang Wu
CPC classification number: G11C11/2275 , G11C11/223 , G11C11/2273 , H10B51/30 , H10B51/40
Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.
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公开(公告)号：US11922984B2
公开(公告)日：2024-03-05
申请号：US17949305
申请日：2022-09-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minhee Cho , Woobin Song , Hyunmog Park , Sangkil Lee
CPC classification number: G11C11/005 , G11C11/223 , G11C11/2275 , G11C11/4096 , H10B12/33 , H10B12/50 , H10B51/30 , H10B51/40
Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.
