公开(公告)号：US12079711B2

公开(公告)日：2024-09-03

申请号：US17186598

申请日：2021-02-26

Applicant: Google LLC

Inventor： Uday Kumar Dasari ,  Olivier Temam ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/063 ,  G06F7/50 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G06F17/16 ,  G06N3/04 ,  G06N3/0464 ,  G06N20/00 ,  G11C11/22 ,  G11C11/54 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06N3/063 ,  G06F15/7896 ,  G06N3/04 ,  G06F7/50 ,  G06F13/1668 ,  G06F13/4027 ,  G06F17/16 ,  G06N3/0464 ,  G06N20/00 ,  G11C11/22 ,  G11C11/54 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

公开(公告)号：US12027226B2

公开(公告)日：2024-07-02

申请号：US17810018

申请日：2022-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Navneet K. Jain ,  Sven Beyer

IPC: G11C16/04 ,  G11C5/06 ,  G11C11/22 ,  G11C13/00

CPC classification number: G11C5/063 ,  G11C11/22 ,  G11C13/0028 ,  G11C13/0069

Abstract: The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

公开(公告)号：US11829775B2

公开(公告)日：2023-11-28

申请号：US17876321

申请日：2022-07-28

Applicant: NUMEM Inc.

Inventor： Eric Hall ,  Doug Smith ,  Nicholas T. Hendrickson ,  Jack Guedj

IPC: G06F9/4401 ,  G11C11/16 ,  G11C11/22 ,  G11C13/00

CPC classification number: G06F9/4418 ,  G11C11/16 ,  G11C11/22 ,  G11C13/0004

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

公开(公告)号：US20190237470A1

公开(公告)日：2019-08-01

申请号：US15884725

申请日：2018-01-31

Applicant: SanDisk Technologies LLC

Inventor： Teruyuki Mine ,  Christopher J. Petti

IPC: H01L27/1159 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11597 ,  G11C11/22 ,  H01L29/51

CPC classification number: H01L27/1159 ,  G11C11/22 ,  H01L27/11597 ,  H01L29/516 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391

Abstract: A memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.

公开(公告)号：US20190214390A1

公开(公告)日：2019-07-11

申请号：US16356464

申请日：2019-03-18

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy

IPC: H01L27/10 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/101 ,  G11C11/22 ,  G11C2213/70 ,  H01L27/11502 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.

公开(公告)号：US20190139591A1

公开(公告)日：2019-05-09

申请号：US16184827

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  H01L27/11507 ,  G11C11/56 ,  G11C14/00

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/5657 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

公开(公告)号：US20180323214A1

公开(公告)日：2018-11-08

申请号：US16020712

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L29/49 ,  H01L27/11585 ,  H01L21/28 ,  H01L29/51 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/11582

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US10082964B2

公开(公告)日：2018-09-25

申请号：US15140073

申请日：2016-04-27

Applicant: Micron Technology, Inc.

Inventor： Kazuhiko Kajigaya

IPC: G06F3/06 ,  G11C7/06 ,  G11C7/12 ,  G11C11/22 ,  G06F12/0806

CPC classification number: G06F3/0616 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0806 ,  G06F2212/1036 ,  G06F2212/62 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/22 ,  G11C11/223 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275

Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

公开(公告)号：US20180269216A1

公开(公告)日：2018-09-20

申请号：US15861055

申请日：2018-01-03

Applicant: SK hynix Inc.

Inventor： Sanghun LEE

IPC: H01L27/11502 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/11502 ,  G11C11/22 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/54 ,  H01L27/11507 ,  H01L27/2418 ,  H01L27/2463 ,  H01L28/55 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1625

Abstract: A ferroelectric memory device includes a first electrode layer disposed on a substrate, a first tunnel barrier layer disposed on the first electrode layer, a second electrode layer disposed on the first tunnel barrier layer, a second tunnel barrier layer disposed on the second electrode layer, and a third electrode layer disposed on the second tunnel barrier layer. Any one of the first and second tunnel barrier layers includes a ferroelectric material.

公开(公告)号：US20180190338A1

公开(公告)日：2018-07-05

申请号：US15829004

申请日：2017-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Seung Hyuk Kang

IPC: G11C11/22 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/49 ,  H01L29/47 ,  H01L29/51 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/223 ,  G11C13/003 ,  H01L21/02148 ,  H01L21/02197 ,  H01L21/02532 ,  H01L21/28291 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1159 ,  H01L29/16 ,  H01L29/47 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/66765 ,  H01L29/6684 ,  H01L29/7839 ,  H01L29/78391 ,  H01L29/78669 ,  H01L29/78678

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.