公开(公告)号：US10347579B2

公开(公告)日：2019-07-09

申请号：US15825231

申请日：2017-11-29

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu

IPC: H01L23/528 ,  H01L23/532 ,  H01L31/09 ,  H01L21/768 ,  H01L23/50

Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.

公开(公告)号：US10283526B2

公开(公告)日：2019-05-07

申请号：US15386501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu

IPC: H01L27/10 ,  H01L27/118 ,  H01L21/8234 ,  H01L23/50 ,  H01L23/538 ,  H01L23/528 ,  H01L27/02

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

公开(公告)号：US10062763B2

公开(公告)日：2018-08-28

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Haining Yang ,  Yanxiang Liu ,  Jeffrey Junhao Xu

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

公开(公告)号：US20180190338A1

公开(公告)日：2018-07-05

申请号：US15829004

申请日：2017-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Seung Hyuk Kang

IPC: G11C11/22 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/49 ,  H01L29/47 ,  H01L29/51 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/223 ,  G11C13/003 ,  H01L21/02148 ,  H01L21/02197 ,  H01L21/02532 ,  H01L21/28291 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1159 ,  H01L29/16 ,  H01L29/47 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/66765 ,  H01L29/6684 ,  H01L29/7839 ,  H01L29/78391 ,  H01L29/78669 ,  H01L29/78678

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.

公开(公告)号：US20180175060A1

公开(公告)日：2018-06-21

申请号：US15386501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu

IPC: H01L27/118 ,  H01L21/8234 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

公开(公告)号：US20180033729A1

公开(公告)日：2018-02-01

申请号：US15634039

申请日：2017-06-27

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L23/5283 ,  G06F17/5072 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53257 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US20170271202A1

公开(公告)日：2017-09-21

申请号：US15229535

申请日：2016-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/49827 ,  H01L23/49894

Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

公开(公告)号：US20170207313A1

公开(公告)日：2017-07-20

申请号：US15213879

申请日：2016-07-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  Peijie Feng ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures. The conductive structure width can also be recessed with regard to width of nanowire structures in the nanowire channel structure to allow for a thicker metal gate to lower the gate resistance, while providing excellent electrostatic gate control of the channel.

公开(公告)号：US20170140986A1

公开(公告)日：2017-05-18

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.