公开(公告)号：US12019905B2

公开(公告)日：2024-06-25

申请号：US17816285

申请日：2022-07-29

申请人： QUALCOMM Incorporated

发明人： Zhongze Wang ,  Mustafa Badaroglu

IPC分类号： G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

摘要： Certain aspects generally relate to performing machine learning tasks, and in particular, to computation-in-memory architectures and operations. One aspect provides a circuit for in-memory computation. The circuit generally includes multiple bit-lines, multiple word-lines, an array of compute-in-memory cells, and a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines. Each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network.

公开(公告)号：US20230238325A1

公开(公告)日：2023-07-27

申请号：US17648981

申请日：2022-01-26

申请人： QUALCOMM Incorporated

发明人： Mustafa Badaroglu ,  Zhongze Wang

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L27/092 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5223

摘要： An integrated circuit includes a trench power rail to reduce resistance in a power rail or avoid an increase in resistance of a power rail as a result of the metal tracks being reduced in size as the technology node size is reduced. The trench power rail is formed in isolation regions between cell circuits. A cell isolation trench in the isolation region provides additional volume in which to dispose additional metal material for forming the trench power rail to increase its cross-sectional area. The trench power rail extends through a via layer to a metal layer, including signal interconnects. The trench power rail extends in a width direction out of the cell isolation trench in the via layer to couple to trench contacts of the adjacent cell circuits without vertical interconnect accesses (vias). A high-K dielectric layer can selectively isolate the trench power rail from the cell circuits.

公开(公告)号：US11581037B2

公开(公告)日：2023-02-14

申请号：US17341797

申请日：2021-06-08

申请人： QUALCOMM Incorporated

发明人： Xiaonan Chen ,  Zhongze Wang ,  Yandong Gao ,  Mustafa Badaroglu

IPC分类号： G11C11/419 ,  G11C11/4094 ,  G06F7/544 ,  G11C11/4091 ,  G06N3/063 ,  G11C11/4097

摘要： Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

公开(公告)号：US11494629B2

公开(公告)日：2022-11-08

申请号：US16669855

申请日：2019-10-31

申请人： QUALCOMM Incorporated

发明人： Zhongze Wang ,  Xia Li ,  Xiaochun Zhu

IPC分类号： G11C16/08 ,  G06N3/063 ,  G11C11/419 ,  G11C11/412 ,  G11C11/21

摘要： Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

公开(公告)号：US10964380B1

公开(公告)日：2021-03-30

申请号：US16784149

申请日：2020-02-06

申请人： QUALCOMM Incorporated

发明人： Zhongze Wang ,  Yandong Gao ,  Xia Li ,  Ye Lu ,  Xiaochun Zhu ,  Xiaonan Chen

IPC分类号： G11C11/41 ,  G11C11/412 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

摘要： A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：US10194529B2

公开(公告)日：2019-01-29

申请号：US15268479

申请日：2016-09-16

申请人： QUALCOMM Incorporated

发明人： Zhongze Wang ,  Guoqing Chen

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F17/00 ,  H01L23/532

摘要： A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.

公开(公告)号：US09786356B2

公开(公告)日：2017-10-10

申请号：US14611056

申请日：2015-01-30

申请人： QUALCOMM Incorporated

发明人： Zhongze Wang ,  Niladri Narayan Mojumder ,  Jonathan Liu ,  Choh Fei Yeap

IPC分类号： G11C29/00 ,  G11C11/417 ,  G06F11/07 ,  G11C29/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C11/417 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

摘要： A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.

公开(公告)号：US09666481B2

公开(公告)日：2017-05-30

申请号：US15141198

申请日：2016-04-28

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20170110364A1

公开(公告)日：2017-04-20

申请号：US15390405

申请日：2016-12-23

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

公开(公告)号：US09576801B2

公开(公告)日：2017-02-21

申请号：US14556983

申请日：2014-12-01

申请人： QUALCOMM Incorporated

发明人： Xia Li ,  Jeffrey Junhao Xu ,  Zhongze Wang ,  Bin Yang ,  Xiaonan Chen ,  Yu Lu

IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  G11C16/04

CPC分类号： H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

摘要： Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

摘要翻译： 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，在非易失性存储器件中被实现为铁电偶极子层。