公开(公告)号：US09773567B1

公开(公告)日：2017-09-26

申请号：US15439086

申请日：2017-02-22

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Guoqing Chen ,  Paul Hoayun

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3422

Abstract: A method and apparatus for balancing voltage stress at a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory array is disclosed. A particular cell of the SONOS flash memory array is selected for programming. A first voltage stress associated with a first SONOS transistor is determined if the particular cell is programmed. The first SONOS transistor is included in a first unselected cell of the SONOS flash memory array. A second voltage stress associated with a second SONOS transistor is determined if the particular cell is programmed. The first voltage stress and the second voltage stress are balanced prior to programming the particular cell.

公开(公告)号：US20200328350A1

公开(公告)日：2020-10-15

申请号：US16382880

申请日：2019-04-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Guoqing Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: An RRAM device is disclosed, having reduced area without increased performance variation, formed by employing a bounded filament formation region in which an oxide layer is thinner and an implanted ion concentration is higher than in a peripheral region of the oxide layer surrounding the bounded filament formation region. Filament formation is controlled to occur in a bounded region having a reduced area by thinning the oxide layer in the bounded region to increase an electric field strength in the bounded region. Defects in the bounded region are subject to greater force from the electric field than defects in the peripheral region. By implanting additional mobile ions or other ion species in the bounded region by an accurately controlled process, a higher concentration of defects is introduced into the bounded region to promote filament formation. Memory elements based on the RRAM device are formed at higher density and lower cost.

公开(公告)号：US10194529B2

公开(公告)日：2019-01-29

申请号：US15268479

申请日：2016-09-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Guoqing Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04 ,  H01L23/522 ,  H01L23/528 ,  H01F17/00 ,  H01L23/532

Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.

公开(公告)号：US20200328253A1

公开(公告)日：2020-10-15

申请号：US16382904

申请日：2019-04-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Guoqing Chen

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  G11C13/00 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L21/265

Abstract: A metal-insulator-semiconductor (MIS) resistive random access memory (RRAM) (MIS RRAM) device and MIS RRAM bit cell circuit are disclosed. A RRAM bit cell includes a RRAM device that can store a memory state and an access transistor to control access to the RRAM device. The RRAM device stores data as an electrical resistance formed in an oxide layer by applying a voltage differential between the top and bottom electrodes through the access transistor to generate an electric field in the oxide layer. This structure is similar to a metal gate formed over a channel region of a transistor. Forming the bottom electrode of the MIS RRAM device in a semiconductor structure may allow the dimensions of the electrodes of the MIS RRAM device to be scaled down to the dimensions of a transistor gate, because the MIS RRAM device structure can be fabricated with the transistor in a compatible process.

公开(公告)号：US20180082776A1

公开(公告)日：2018-03-22

申请号：US15268479

申请日：2016-09-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Guoqing Chen

IPC: H01F27/28 ,  H01F27/29 ,  H01F41/04

CPC classification number: H05K1/115 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/29 ,  H01F41/042 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5329 ,  H05K3/4038 ,  H05K3/421

Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.