公开(公告)号：US11411092B2

公开(公告)日：2022-08-09

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Peijie Feng ,  Chenjie Tang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423 ,  H01L21/02 ,  H01L21/764

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20210320197A1

公开(公告)日：2021-10-14

申请号：US16844479

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Chenjie Tang ,  Ye Lu ,  Peijie Feng ,  Junjing Bao

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

公开(公告)号：US10861793B2

公开(公告)日：2020-12-08

申请号：US16051525

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Haitao Cheng ,  Ye Lu ,  Chao Song

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/58 ,  H01L23/522

Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

公开(公告)号：US10756085B2

公开(公告)日：2020-08-25

申请号：US15835810

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Bin Yang ,  Lixin Ge

IPC: H01L27/088 ,  H01L27/06 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/762 ,  H03K19/0185 ,  H01L21/8234 ,  G06F30/398 ,  H01L27/092

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

公开(公告)号：US10714582B2

公开(公告)日：2020-07-14

申请号：US16002459

申请日：2018-06-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Ye Lu ,  Lixin Ge

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L29/423 ,  H01L29/49

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

公开(公告)号：US10665678B2

公开(公告)日：2020-05-26

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US10263080B2

公开(公告)日：2019-04-16

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Junjing Bao ,  Bin Yang ,  Lixin Ge ,  Yun Yue

IPC: H01L29/66 ,  H01L29/16 ,  H01L21/02 ,  H01L29/10 ,  H01L29/72 ,  H01L29/78

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US11289365B2

公开(公告)日：2022-03-29

申请号：US16676663

申请日：2019-11-07

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Ye Lu ,  Haitao Cheng

IPC: H01L21/64 ,  H01L29/06 ,  H01L49/02 ,  H01L21/764

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device including an air gap underneath passive devices. The semiconductor device generally includes a substrate layer, a passive device layer, and a dielectric layer disposed between the substrate layer and the passive device layer, wherein the dielectric layer includes an air gap disposed beneath at least one passive device in the passive device layer.

公开(公告)号：US20210349689A1

公开(公告)日：2021-11-11

申请号：US16868202

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Zhongze Wang ,  Periannan Chidambaram

IPC: G06F7/523 ,  G11C11/412 ,  G11C11/419

Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.

公开(公告)号：US20210280582A1

公开(公告)日：2021-09-09

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/06 ,  H01L29/10

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.