公开(公告)号：US11444201B2

公开(公告)日：2022-09-13

申请号：US16831010

申请日：2020-03-26

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Kwanyong Lim ,  Youseok Suh ,  Hyunwoo Park

IPC: H01L21/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088

Abstract: Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.

公开(公告)号：US11296083B2

公开(公告)日：2022-04-05

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

公开(公告)号：US11145654B2

公开(公告)日：2021-10-12

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong Lim ,  Stanley Seungchul Song ,  Jun Yuan ,  Kern Rim

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

公开(公告)号：US20210143153A1

公开(公告)日：2021-05-13

申请号：US16682788

申请日：2019-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong Lim ,  Hyunwoo Park ,  Youn Sung Choi ,  Youseok Suh

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Fin Field-Effect Transistor (FET) (FinFET) circuits employing a replacement N-type FET (NFET) source/drains (S/D) are disclosed. The disclosed method for forming a FinFET circuit includes forming two P-type epitaxial S/Ds (epi-S/Ds), one on the fin in the P-type diffusion region and one on the fin in the N-type diffusion region, forming a boundary layer to isolate the P-type epi-S/Ds, and then replacing the P-type epi-S/D under the boundary layer in the N-type diffusion region with an N-type epi-S/D. A mask is employed in steps for replacing the P-type epi-S/D with an N-type epi-S/D in the disclosed method but differs from the mask in the previous method such that vulnerability to variations thereof is reduced. The mask in the disclosed method has a larger acceptable range of variation within which no defects are created, so the disclosed method is less vulnerable to process variation and prevents short defects.

公开(公告)号：US20190312025A1

公开(公告)日：2019-10-10

申请号：US15947114

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Youseok Suh ,  Kwanyong Lim

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.

公开(公告)号：US20240321860A1

公开(公告)日：2024-09-26

申请号：US18189045

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao ,  Hyunwoo Park ,  Kwanyong Lim

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H03K19/0948

CPC classification number: H01L27/0207 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H03K19/0948

Abstract: Logic circuits are implemented in row cell circuits that include diffusion regions. Each diffusion region portion is employed by a transistor in a cell circuit. A current capacity of each transistor depends on a width of the diffusion region portion. A first diffusion region portion and a second diffusion region portion having different widths intersect along an axis, where the diffusion region of a row cell circuit abruptly transitions (e.g., at a square corner) in width. A gate disposed over the diffusion region along the intersection includes a first side on the first diffusion region portion and a second side on the second diffusion region portion. The transition occurring between the first side and the second side of the gate may be achieved by square corner features formed in the diffusion region. Such features were not previously achievable at small technology nodes due to mask pattern limitations.

公开(公告)号：US20210280582A1

公开(公告)日：2021-09-09

申请号：US16811762

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Lixin Ge ,  Kwanyong Lim ,  Jun Chen

IPC: H01L27/092 ,  H01L23/522 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/06 ,  H01L29/10

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

公开(公告)号：US11075206B2

公开(公告)日：2021-07-27

申请号：US16220096

申请日：2018-12-14

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong Lim ,  Youn Sung Choi ,  Ukjin Roh

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08

Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.

公开(公告)号：US10600774B2

公开(公告)日：2020-03-24

申请号：US15947114

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung Choi ,  Youseok Suh ,  Kwanyong Lim

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.