公开(公告)号：US10332881B1

公开(公告)日：2019-06-25

申请号：US16104544

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L21/02 ,  H01L27/02 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.

公开(公告)号：US20190107569A1

公开(公告)日：2019-04-11

申请号：US15730486

申请日：2017-10-11

Applicant: QUALCOMM Incorporated

Inventor： David Kidd ,  Ardavan Moassessi ,  Angelo Pinto ,  Albert Kumar ,  Yi Lou ,  Bipin Duggal ,  Amar Gulhane ,  Michael Bourland ,  Mustafa Badaroglu ,  Paul Penzes

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/36 ,  H01L21/66

Abstract: Aspects of the disclosure includes a transistor-under-test (TUT) to charge/discharge a capacitor; changing an oscillation state when a capacitor voltage crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT; and generating a digital representation of a TUT current associated with a relaxation oscillator period of the relaxation oscillator waveform. For example, a measurement tile includes a pulse generator to sustain the relaxation oscillator waveform with the relaxation oscillator period associated with an inverse TUT current; and a precharger charging a capacitor and the TUT charging/discharging the capacitor, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT in accordance with discharging and charging the capacitor.

公开(公告)号：US10157992B2

公开(公告)日：2018-12-18

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/08

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09871121B2

公开(公告)日：2018-01-16

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09824936B2

公开(公告)日：2017-11-21

申请号：US15293213

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  B82Y10/00 ,  H01L27/088

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

公开(公告)号：US20170186846A1

公开(公告)日：2017-06-29

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09570509B2

公开(公告)日：2017-02-14

申请号：US14609169

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract translation: 半导体器件包括第一磁隧道结（MTJ）器件，第二MTJ器件和顶电极。 第一MTJ装置包括阻挡层。 第二MTJ装置包括阻挡层。 顶部电极耦合到第一MTJ装置和第二MTJ装置。

公开(公告)号：US09564518B2

公开(公告)日：2017-02-07

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。

公开(公告)号：US12019905B2

公开(公告)日：2024-06-25

申请号：US17816285

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Mustafa Badaroglu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Certain aspects generally relate to performing machine learning tasks, and in particular, to computation-in-memory architectures and operations. One aspect provides a circuit for in-memory computation. The circuit generally includes multiple bit-lines, multiple word-lines, an array of compute-in-memory cells, and a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines. Each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network.

公开(公告)号：US20230238325A1

公开(公告)日：2023-07-27

申请号：US17648981

申请日：2022-01-26

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Zhongze Wang

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5223

Abstract: An integrated circuit includes a trench power rail to reduce resistance in a power rail or avoid an increase in resistance of a power rail as a result of the metal tracks being reduced in size as the technology node size is reduced. The trench power rail is formed in isolation regions between cell circuits. A cell isolation trench in the isolation region provides additional volume in which to dispose additional metal material for forming the trench power rail to increase its cross-sectional area. The trench power rail extends through a via layer to a metal layer, including signal interconnects. The trench power rail extends in a width direction out of the cell isolation trench in the via layer to couple to trench contacts of the adjacent cell circuits without vertical interconnect accesses (vias). A high-K dielectric layer can selectively isolate the trench power rail from the cell circuits.