公开(公告)号：US10903240B2

公开(公告)日：2021-01-26

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daniel Daeik Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L23/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20190067435A1

公开(公告)日：2019-02-28

申请号：US16171061

申请日：2018-10-25

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/49 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09298946B2

公开(公告)日：2016-03-29

申请号：US14072735

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C17/02 ,  G06F21/70 ,  G06F1/26 ,  G11C11/16 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00

CPC classification number: G06F21/70 ,  G06F1/26 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C17/02 ,  G11C17/14 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆的功能的方法，其包括提供金属 - 绝缘体 - 金属（MIM）器件的阵列，其中MIM器件被配置为表示第一电阻状态或第二电阻状态，并且多个 MIM器件最初处于第一电阻状态。 MIM器件具有大于第一电压且小于第二电压的随机击穿电压，其中击穿电压表示使MIM器件从第一电阻状态转变到第二电阻状态的电压。 该方法还包括向MIM器件施加信号线电压以使MIM器件的一部分随机击穿并从第一电阻状态转变到第二电阻状态，信号线电压大于第一电压并小于 第二电压。

公开(公告)号：US08987062B2

公开(公告)日：2015-03-24

申请号：US14056212

申请日：2013-10-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Matthew Michael Nowak ,  Thomas Robert Toms

IPC: H01L23/24 ,  H05K7/20 ,  H01L23/38 ,  H01L25/065

CPC classification number: H05K7/20 ,  H01L23/38 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.

Abstract translation: 可以通过在堆叠的IC器件内构造一个或多个有源温度控制器件来提高层叠IC器件中的导热性。 在一个实施例中，控制装置是诸如珀耳帖装置之类的热电（TE）装置。 然后可根据需要选择性地控制TE器件去除或加热，以将堆叠的IC器件保持在规定的温度范围内。 活性温度控制元件可以是在堆叠的IC器件中产生的P-N结，并且可以根据需要用于横向和/或垂直地移动热量。

公开(公告)号：US20150071432A1

公开(公告)日：2015-03-12

申请号：US14077093

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David Merrill Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to least one physically unclonable function based on an array of magnetoresistive random-access memory (MRAM) cells. A challenge to the array of MRAM cells may identify some of the cells to be used for the physically unclonable function. Each MRAM cell may include a plurality of magnetic tunnel junctions (MTJs), where the MTJs may exhibit distinct resistances due to manufacturing or fabrication variations. A response to the challenge may be obtained for each cell by using the resistance(s) of one or both of the MTJs for a cell to obtain a value that serves as the response for that cell. The responses for a plurality of cells may be at least partially mapped to provide a unique identifier for the array. The responses generated from the array of cells may serve as a physically unclonable function that may be used to uniquely identify an electronic device.

Abstract translation: 一个特征涉及基于磁阻随机存取存储器（MRAM）单元阵列的至少一个物理上不可克隆的功能。 对MRAM单元阵列的挑战可能会识别要用于物理不可克隆功能的一些单元格。 每个MRAM单元可以包括多个磁隧道结（MTJ），其中MTJ可能由于制造或制造变化而呈现出不同的电阻。 可以通过使用用于单元的MTJ中的一个或两个的电阻来获得用作该单元的响应的值，为每个单元获得对该挑战的响应。 可以至少部分地映射多个小区的响应以提供阵列的唯一标识符。 从单元阵列产生的响应可以用作可以用于唯一地识别电子设备的物理上不可克隆的功能。

公开(公告)号：US20140098602A1

公开(公告)日：2014-04-10

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。

公开(公告)号：US09906318B2

公开(公告)日：2018-02-27

申请号：US14682023

申请日：2015-04-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Ryan Scott C. Spring ,  Xiangdong Zhang

IPC: H04J1/00 ,  H04J1/08 ,  H03H7/46 ,  H04B1/00

CPC classification number: H04J1/08 ,  H03H7/465 ,  H03H2240/00 ,  H03H2250/00 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/0064

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

公开(公告)号：US09768109B2

公开(公告)日：2017-09-19

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/306

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US20170140986A1

公开(公告)日：2017-05-18

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US20170084628A1

公开(公告)日：2017-03-23

申请号：US14858203

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/86

Abstract: Substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers are disclosed. In this regard, a bulk semiconductor wafer is provided that includes a bulk body, one or more transistors formed in the bulk body, and deep trenches formed between the transistors formed in the bulk body to provide isolation between the transistors. To prevent the bulk body from electrically interconnecting the transistors, the bulk body is thinned near, at, or beyond a back side of the deep trenches formed in the bulk body to form separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate is bonded to the bulk semiconductor device to form an SOI wafer. In this manner, residual bulk bodies of the transistors in the SOI wafer are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors.