公开(公告)号：US09728718B2

公开(公告)日：2017-08-08

申请号：US15389322

申请日：2016-12-22

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

公开(公告)号：US20170140986A1

公开(公告)日：2017-05-18

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US20160293485A1

公开(公告)日：2016-10-06

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract translation: 翅片型半导体器件包括栅极结构和源极/漏极结构。 翅片型半导体器件还包括耦合到栅极结构的栅极硬掩模结构。 门硬掩模结构包括第一材料。 翅片型半导体器件还包括耦合到源极/漏极结构的源极/漏极硬掩模结构。 源极/漏极硬掩模结构包括第二材料。

公开(公告)号：US20160049487A1

公开(公告)日：2016-02-18

申请号：US14670268

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/785

Abstract: A device includes a first structure and a second structure. The second structure is separated from the first structure by a cavity. The device further includes a seal material, an etch stop material defining an etched region, and a self-aligned contact (SAC). The seal material is configured to seal the cavity, and the SAC is formed within the etched region. The SAC adjoins the seal material, the etch stop material, or a combination thereof.

Abstract translation: 一种装置包括第一结构和第二结构。 第二结构通过空腔与第一结构分离。 该装置还包括密封材料，限定蚀刻区域的蚀刻停止材料和自对准接触（SAC）。 密封材料构造成密封空腔，并且在蚀刻区域内形成SAC。 SAC邻接密封材料，蚀刻停止材料或其组合。

公开(公告)号：US10157992B2

公开(公告)日：2018-12-18

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/08

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09871121B2

公开(公告)日：2018-01-16

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09824936B2

公开(公告)日：2017-11-21

申请号：US15293213

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  B82Y10/00 ,  H01L27/088

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

公开(公告)号：US20170186846A1

公开(公告)日：2017-06-29

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09570509B2

公开(公告)日：2017-02-14

申请号：US14609169

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract translation: 半导体器件包括第一磁隧道结（MTJ）器件，第二MTJ器件和顶电极。 第一MTJ装置包括阻挡层。 第二MTJ装置包括阻挡层。 顶部电极耦合到第一MTJ装置和第二MTJ装置。

公开(公告)号：US09564518B2

公开(公告)日：2017-02-07

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。